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Soby Mathew802f8652014-08-14 16:19:29 +01001#
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +01002# Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathew802f8652014-08-14 16:19:29 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Soby Mathew802f8652014-08-14 16:19:29 +01005#
6
Soby Mathew937488b2014-09-22 14:13:34 +01007# Cortex A57 specific optimisation to skip L1 cache flush when
8# cluster is powered down.
9SKIP_A57_L1_FLUSH_PWR_DWN ?=0
10
Sandrine Bailleuxd4817592016-01-13 14:57:38 +000011# Flag to disable the cache non-temporal hint.
12# It is enabled by default.
13A53_DISABLE_NON_TEMPORAL_HINT ?=1
14
15# Flag to disable the cache non-temporal hint.
16# It is enabled by default.
17A57_DISABLE_NON_TEMPORAL_HINT ?=1
18
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000019WORKAROUND_CVE_2017_5715 ?=1
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010020WORKAROUND_CVE_2018_3639 ?=1
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010021DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000022
Soby Mathew937488b2014-09-22 14:13:34 +010023# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
24$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
25$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
26
Sandrine Bailleuxd4817592016-01-13 14:57:38 +000027# Process A53_DISABLE_NON_TEMPORAL_HINT flag
28$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT))
29$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT))
30
31# Process A57_DISABLE_NON_TEMPORAL_HINT flag
32$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT))
33$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT))
34
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000035# Process WORKAROUND_CVE_2017_5715 flag
36$(eval $(call assert_boolean,WORKAROUND_CVE_2017_5715))
37$(eval $(call add_define,WORKAROUND_CVE_2017_5715))
Soby Mathew937488b2014-09-22 14:13:34 +010038
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010039# Process WORKAROUND_CVE_2018_3639 flag
40$(eval $(call assert_boolean,WORKAROUND_CVE_2018_3639))
41$(eval $(call add_define,WORKAROUND_CVE_2018_3639))
42
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010043$(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639))
44$(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639))
45
46ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
47 ifeq (${WORKAROUND_CVE_2018_3639},0)
48 $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")
49 endif
50endif
51
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010052# CPU Errata Build flags.
53# These should be enabled by the platform if the erratum workaround needs to be
54# applied.
Soby Mathew802f8652014-08-14 16:19:29 +010055
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010056# Flag to apply erratum 826319 workaround during reset. This erratum applies
57# only to revision <= r0p2 of the Cortex A53 cpu.
developer4fceaca2015-07-29 20:55:31 +080058ERRATA_A53_826319 ?=0
59
Douglas Raillardd56fb042017-06-19 15:38:02 +010060# Flag to apply erratum 835769 workaround at compile and link time. This
61# erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this
62# workaround can lead the linker to create "*.stub" sections.
63ERRATA_A53_835769 ?=0
64
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010065# Flag to apply erratum 836870 workaround during reset. This erratum applies
66# only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this
Douglas Raillardc847f662017-02-15 17:38:43 +000067# erratum workaround is enabled by default in hardware.
developer4fceaca2015-07-29 20:55:31 +080068ERRATA_A53_836870 ?=0
69
Douglas Raillardd56fb042017-06-19 15:38:02 +010070# Flag to apply erratum 843419 workaround at link time.
71# This erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this
72# workaround could lead the linker to emit "*.stub" sections which are 4kB
73# aligned.
74ERRATA_A53_843419 ?=0
75
Andre Przywara00eefd92016-10-06 16:54:53 +010076# Flag to apply errata 855873 during reset. This errata applies to all
77# revisions of the Cortex A53 CPU, but this firmware workaround only works
78# for revisions r0p3 and higher. Earlier revisions are taken care
79# of by the rich OS.
80ERRATA_A53_855873 ?=0
81
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010082# Flag to apply erratum 806969 workaround during reset. This erratum applies
83# only to revision r0p0 of the Cortex A57 cpu.
Soby Mathew802f8652014-08-14 16:19:29 +010084ERRATA_A57_806969 ?=0
85
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +000086# Flag to apply erratum 813419 workaround during reset. This erratum applies
87# only to revision r0p0 of the Cortex A57 cpu.
88ERRATA_A57_813419 ?=0
89
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010090# Flag to apply erratum 813420 workaround during reset. This erratum applies
91# only to revision r0p0 of the Cortex A57 cpu.
Soby Mathew802f8652014-08-14 16:19:29 +010092ERRATA_A57_813420 ?=0
93
Sandrine Bailleuxa7e0c532016-04-14 13:32:31 +010094# Flag to apply erratum 826974 workaround during reset. This erratum applies
95# only to revision <= r1p1 of the Cortex A57 cpu.
96ERRATA_A57_826974 ?=0
97
Sandrine Bailleuxadcbd552016-04-14 14:24:13 +010098# Flag to apply erratum 826977 workaround during reset. This erratum applies
99# only to revision <= r1p1 of the Cortex A57 cpu.
100ERRATA_A57_826977 ?=0
101
Sandrine Bailleuxc11116f2016-04-14 14:04:48 +0100102# Flag to apply erratum 828024 workaround during reset. This erratum applies
103# only to revision <= r1p1 of the Cortex A57 cpu.
104ERRATA_A57_828024 ?=0
105
Sandrine Bailleux48cbe852016-04-14 14:18:07 +0100106# Flag to apply erratum 829520 workaround during reset. This erratum applies
107# only to revision <= r1p2 of the Cortex A57 cpu.
108ERRATA_A57_829520 ?=0
109
Sandrine Bailleux143ef1a2016-04-21 11:10:52 +0100110# Flag to apply erratum 833471 workaround during reset. This erratum applies
111# only to revision <= r1p2 of the Cortex A57 cpu.
112ERRATA_A57_833471 ?=0
113
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +0100114# Flag to apply erratum 855972 workaround during reset. This erratum applies
115# only to revision <= r1p3 of the Cortex A57 cpu.
116ERRATA_A57_859972 ?=0
117
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100118# Flag to apply erratum 855971 workaround during reset. This erratum applies
119# only to revision <= r0p3 of the Cortex A72 cpu.
120ERRATA_A72_859971 ?=0
121
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100122# Flag to apply T32 CLREX workaround during reset. This erratum applies
123# only to r0p0 and r1p0 of the Ares cpu.
124ERRATA_ARES_1043202 ?=1
125
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100126# Flag to apply DSU erratum 936184. This erratum applies to DSUs containing
127# the ACP interface and revision < r2p0. Applying the workaround results in
128# higher DSU power consumption on idle.
129ERRATA_DSU_936184 ?=0
130
developer4fceaca2015-07-29 20:55:31 +0800131# Process ERRATA_A53_826319 flag
132$(eval $(call assert_boolean,ERRATA_A53_826319))
133$(eval $(call add_define,ERRATA_A53_826319))
134
Douglas Raillardd56fb042017-06-19 15:38:02 +0100135# Process ERRATA_A53_835769 flag
136$(eval $(call assert_boolean,ERRATA_A53_835769))
137$(eval $(call add_define,ERRATA_A53_835769))
138
developer4fceaca2015-07-29 20:55:31 +0800139# Process ERRATA_A53_836870 flag
140$(eval $(call assert_boolean,ERRATA_A53_836870))
141$(eval $(call add_define,ERRATA_A53_836870))
142
Douglas Raillardd56fb042017-06-19 15:38:02 +0100143# Process ERRATA_A53_843419 flag
144$(eval $(call assert_boolean,ERRATA_A53_843419))
145$(eval $(call add_define,ERRATA_A53_843419))
146
Andre Przywara00eefd92016-10-06 16:54:53 +0100147# Process ERRATA_A53_855873 flag
148$(eval $(call assert_boolean,ERRATA_A53_855873))
149$(eval $(call add_define,ERRATA_A53_855873))
150
Soby Mathew802f8652014-08-14 16:19:29 +0100151# Process ERRATA_A57_806969 flag
152$(eval $(call assert_boolean,ERRATA_A57_806969))
153$(eval $(call add_define,ERRATA_A57_806969))
154
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000155# Process ERRATA_A57_813419 flag
156$(eval $(call assert_boolean,ERRATA_A57_813419))
157$(eval $(call add_define,ERRATA_A57_813419))
158
Soby Mathew802f8652014-08-14 16:19:29 +0100159# Process ERRATA_A57_813420 flag
160$(eval $(call assert_boolean,ERRATA_A57_813420))
161$(eval $(call add_define,ERRATA_A57_813420))
Sandrine Bailleuxa7e0c532016-04-14 13:32:31 +0100162
163# Process ERRATA_A57_826974 flag
164$(eval $(call assert_boolean,ERRATA_A57_826974))
165$(eval $(call add_define,ERRATA_A57_826974))
Sandrine Bailleuxc11116f2016-04-14 14:04:48 +0100166
Sandrine Bailleuxadcbd552016-04-14 14:24:13 +0100167# Process ERRATA_A57_826977 flag
168$(eval $(call assert_boolean,ERRATA_A57_826977))
169$(eval $(call add_define,ERRATA_A57_826977))
170
Sandrine Bailleuxc11116f2016-04-14 14:04:48 +0100171# Process ERRATA_A57_828024 flag
172$(eval $(call assert_boolean,ERRATA_A57_828024))
173$(eval $(call add_define,ERRATA_A57_828024))
Sandrine Bailleux48cbe852016-04-14 14:18:07 +0100174
175# Process ERRATA_A57_829520 flag
176$(eval $(call assert_boolean,ERRATA_A57_829520))
177$(eval $(call add_define,ERRATA_A57_829520))
Sandrine Bailleux143ef1a2016-04-21 11:10:52 +0100178
179# Process ERRATA_A57_833471 flag
180$(eval $(call assert_boolean,ERRATA_A57_833471))
181$(eval $(call add_define,ERRATA_A57_833471))
Douglas Raillardd56fb042017-06-19 15:38:02 +0100182
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +0100183# Process ERRATA_A57_859972 flag
184$(eval $(call assert_boolean,ERRATA_A57_859972))
185$(eval $(call add_define,ERRATA_A57_859972))
186
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100187# Process ERRATA_A72_859971 flag
188$(eval $(call assert_boolean,ERRATA_A72_859971))
189$(eval $(call add_define,ERRATA_A72_859971))
190
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100191# Process ERRATA_ARES_1043202 flag
192$(eval $(call assert_boolean,ERRATA_ARES_1043202))
193$(eval $(call add_define,ERRATA_ARES_1043202))
194
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100195# Process ERRATA_DSU_936184 flag
196$(eval $(call assert_boolean,ERRATA_DSU_936184))
197$(eval $(call add_define,ERRATA_DSU_936184))
198
Douglas Raillardd56fb042017-06-19 15:38:02 +0100199# Errata build flags
200ifneq (${ERRATA_A53_843419},0)
Douglas Raillardd0c82732017-06-22 14:44:48 +0100201TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419
Douglas Raillardd56fb042017-06-19 15:38:02 +0100202endif
203
204ifneq (${ERRATA_A53_835769},0)
205TF_CFLAGS_aarch64 += -mfix-cortex-a53-835769
Douglas Raillardd0c82732017-06-22 14:44:48 +0100206TF_LDFLAGS_aarch64 += --fix-cortex-a53-835769
Douglas Raillardd56fb042017-06-19 15:38:02 +0100207endif