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Ghennadi Procopciucf648e5d2024-06-12 09:07:16 +03001/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <drivers/clk.h>
7#include <s32cc-clk-drv.h>
8#include <s32cc-clk-ids.h>
9#include <s32cc-clk-utils.h>
10
11#define S32CC_FXOSC_FREQ (40U * MHZ)
Ghennadi Procopciuce18cf332024-06-12 11:55:32 +030012#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
Ghennadi Procopciuc907f6542024-06-12 12:00:15 +030013#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
Ghennadi Procopciuca6a39e82024-06-12 13:05:05 +030014#define S32CC_A53_FREQ (1U * GHZ)
Ghennadi Procopciucf648e5d2024-06-12 09:07:16 +030015
16int s32cc_init_early_clks(void)
17{
18 int ret;
19
20 s32cc_clk_register_drv();
21
Ghennadi Procopciuc4e4786d2024-06-12 11:17:37 +030022 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC);
23 if (ret != 0) {
24 return ret;
25 }
26
27 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0);
28 if (ret != 0) {
29 return ret;
30 }
31
Ghennadi Procopciucf648e5d2024-06-12 09:07:16 +030032 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL);
33 if (ret != 0) {
34 return ret;
35 }
36
Ghennadi Procopciuce18cf332024-06-12 11:55:32 +030037 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL);
38 if (ret != 0) {
39 return ret;
40 }
41
Ghennadi Procopciuc907f6542024-06-12 12:00:15 +030042 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL);
43 if (ret != 0) {
44 return ret;
45 }
46
Ghennadi Procopciuca6a39e82024-06-12 13:05:05 +030047 ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL);
48 if (ret != 0) {
49 return ret;
50 }
51
Ghennadi Procopciuc9dee8e42024-06-12 09:25:17 +030052 ret = clk_enable(S32CC_CLK_FXOSC);
53 if (ret != 0) {
54 return ret;
55 }
56
Ghennadi Procopciucf648e5d2024-06-12 09:07:16 +030057 return ret;
58}