feat(nxp-clk): set rate for clock muxes
The clock muxes will simply pass the set rate request to the clock
module connected to its source, as they do not alter the frequency.
Change-Id: I5fda8fffa0f46a4be96deac4d6a5a880c9f86ccf
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index ac1f7d0..659cef3 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -11,6 +11,7 @@
#define S32CC_FXOSC_FREQ (40U * MHZ)
#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
+#define S32CC_A53_FREQ (1U * GHZ)
int s32cc_init_early_clks(void)
{
@@ -43,6 +44,11 @@
return ret;
}
+ ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
ret = clk_enable(S32CC_CLK_FXOSC);
if (ret != 0) {
return ret;