blob: 98f30d88cd5232eceaa91cce0bf247b5ea0d4ec2 [file] [log] [blame]
Ghennadi Procopciucf648e5d2024-06-12 09:07:16 +03001/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <drivers/clk.h>
7#include <s32cc-clk-drv.h>
8#include <s32cc-clk-ids.h>
9#include <s32cc-clk-utils.h>
10
11#define S32CC_FXOSC_FREQ (40U * MHZ)
12
13int s32cc_init_early_clks(void)
14{
15 int ret;
16
17 s32cc_clk_register_drv();
18
Ghennadi Procopciuc4e4786d2024-06-12 11:17:37 +030019 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC);
20 if (ret != 0) {
21 return ret;
22 }
23
24 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0);
25 if (ret != 0) {
26 return ret;
27 }
28
Ghennadi Procopciucf648e5d2024-06-12 09:07:16 +030029 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL);
30 if (ret != 0) {
31 return ret;
32 }
33
Ghennadi Procopciuc9dee8e42024-06-12 09:25:17 +030034 ret = clk_enable(S32CC_CLK_FXOSC);
35 if (ret != 0) {
36 return ret;
37 }
38
Ghennadi Procopciucf648e5d2024-06-12 09:07:16 +030039 return ret;
40}