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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -06002 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +00006
Manish V Badarkhe01e9dd22020-08-04 17:13:14 +01007#include <lib/smccc.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +00008#include <platform_def.h>
Manish V Badarkhe01e9dd22020-08-04 17:13:14 +01009#include <services/arm_arch_svc.h>
10
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000011#include <plat/arm/common/plat_arm.h>
Dan Handley9df48042015-03-19 18:58:55 +000012
13/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010014 * Table of memory regions for different BL stages to map using the MMU.
Roberto Vargas344ff022018-10-19 16:44:18 +010015 * This doesn't include Trusted SRAM as setup_page_tables() already takes care
16 * of mapping it.
Dan Handley9df48042015-03-19 18:58:55 +000017 */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090018#ifdef IMAGE_BL1
Dan Handley9df48042015-03-19 18:58:55 +000019const mmap_region_t plat_arm_mmap[] = {
20 ARM_MAP_SHARED_RAM,
Soby Mathew94273572018-03-07 11:32:04 +000021 V2M_MAP_FLASH0_RW,
Dan Handley9df48042015-03-19 18:58:55 +000022 V2M_MAP_IOFPGA,
23 CSS_MAP_DEVICE,
24 SOC_CSS_MAP_DEVICE,
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010025#if TRUSTED_BOARD_BOOT
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010026 /* Map DRAM to authenticate NS_BL2U image. */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010027 ARM_MAP_NS_DRAM1,
28#endif
Dan Handley9df48042015-03-19 18:58:55 +000029 {0}
30};
31#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090032#ifdef IMAGE_BL2
Dan Handley9df48042015-03-19 18:58:55 +000033const mmap_region_t plat_arm_mmap[] = {
34 ARM_MAP_SHARED_RAM,
Soby Mathew94273572018-03-07 11:32:04 +000035 V2M_MAP_FLASH0_RW,
Roberto Vargasa1c16b62017-08-03 09:16:43 +010036#ifdef PLAT_ARM_MEM_PROT_ADDR
37 ARM_V2M_MAP_MEM_PROTECT,
38#endif
Dan Handley9df48042015-03-19 18:58:55 +000039 V2M_MAP_IOFPGA,
40 CSS_MAP_DEVICE,
41 SOC_CSS_MAP_DEVICE,
42 ARM_MAP_NS_DRAM1,
Julius Werner8e0ef0f2019-07-09 14:02:43 -070043#ifdef __aarch64__
Roberto Vargasf8fda102017-08-08 11:27:20 +010044 ARM_MAP_DRAM2,
45#endif
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +010046#ifdef SPD_tspd
Dan Handley9df48042015-03-19 18:58:55 +000047 ARM_MAP_TSP_SEC_MEM,
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +010048#endif
Summer Qin9db8f2e2017-04-24 16:49:28 +010049#ifdef SPD_opteed
Soby Mathew874fc9e2017-09-01 13:43:50 +010050 ARM_MAP_OPTEE_CORE_MEM,
Summer Qin9db8f2e2017-04-24 16:49:28 +010051 ARM_OPTEE_PAGEABLE_LOAD_MEM,
52#endif
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -060053#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
Louis Mayencourt3e7c38a2019-07-31 15:03:44 +010054 ARM_MAP_BL1_RW,
55#endif
Dan Handley9df48042015-03-19 18:58:55 +000056 {0}
57};
58#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090059#ifdef IMAGE_BL2U
Yatharth Kochar3a11eda2015-10-14 15:28:11 +010060const mmap_region_t plat_arm_mmap[] = {
61 ARM_MAP_SHARED_RAM,
62 CSS_MAP_DEVICE,
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010063 CSS_MAP_SCP_BL2U,
64 V2M_MAP_IOFPGA,
Yatharth Kochar3a11eda2015-10-14 15:28:11 +010065 SOC_CSS_MAP_DEVICE,
66 {0}
67};
68#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090069#ifdef IMAGE_BL31
Dan Handley9df48042015-03-19 18:58:55 +000070const mmap_region_t plat_arm_mmap[] = {
71 ARM_MAP_SHARED_RAM,
72 V2M_MAP_IOFPGA,
73 CSS_MAP_DEVICE,
Roberto Vargasa1c16b62017-08-03 09:16:43 +010074#ifdef PLAT_ARM_MEM_PROT_ADDR
75 ARM_V2M_MAP_MEM_PROTECT,
76#endif
Dan Handley9df48042015-03-19 18:58:55 +000077 SOC_CSS_MAP_DEVICE,
Mikael Olsson0232da22021-02-12 17:30:16 +010078 ARM_DTB_DRAM_NS,
Dan Handley9df48042015-03-19 18:58:55 +000079 {0}
80};
81#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090082#ifdef IMAGE_BL32
Dan Handley9df48042015-03-19 18:58:55 +000083const mmap_region_t plat_arm_mmap[] = {
Julius Werner8e0ef0f2019-07-09 14:02:43 -070084#ifndef __aarch64__
Yatharth Kochar2694cba2016-11-14 12:00:41 +000085 ARM_MAP_SHARED_RAM,
Roberto Vargas550eb082018-01-05 16:00:05 +000086#ifdef PLAT_ARM_MEM_PROT_ADDR
87 ARM_V2M_MAP_MEM_PROTECT,
88#endif
Yatharth Kochar2694cba2016-11-14 12:00:41 +000089#endif
Dan Handley9df48042015-03-19 18:58:55 +000090 V2M_MAP_IOFPGA,
91 CSS_MAP_DEVICE,
92 SOC_CSS_MAP_DEVICE,
93 {0}
94};
95#endif
96
97ARM_CASSERT_MMAP
Manish V Badarkhe01e9dd22020-08-04 17:13:14 +010098
99/*****************************************************************************
100 * plat_is_smccc_feature_available() - This function checks whether SMCCC
101 * feature is availabile for platform.
102 * @fid: SMCCC function id
103 *
104 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
105 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
106 *****************************************************************************/
107int32_t plat_is_smccc_feature_available(u_register_t fid)
108{
109 switch (fid) {
110 case SMCCC_ARCH_SOC_ID:
111 return SMC_ARCH_CALL_SUCCESS;
112 default:
113 return SMC_ARCH_CALL_NOT_SUPPORTED;
114 }
115}
116
117/* Get SOC version */
118int32_t plat_get_soc_version(void)
119{
120 return (int32_t)
Yann Gautieree050772021-05-20 14:57:34 +0200121 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
122 ARM_SOC_IDENTIFICATION_CODE) |
123 (JUNO_SOC_ID & SOC_ID_IMPL_DEF_MASK));
Manish V Badarkhe01e9dd22020-08-04 17:13:14 +0100124}
125
126/* Get SOC revision */
127int32_t plat_get_soc_revision(void)
128{
129 unsigned int sys_id;
130
131 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
Yann Gautieree050772021-05-20 14:57:34 +0200132 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
133 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
Manish V Badarkhe01e9dd22020-08-04 17:13:14 +0100134}