Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Zelalem | e8dadb1 | 2020-02-05 14:12:39 -0600 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <string.h> |
| 9 | |
| 10 | #include <platform_def.h> |
| 11 | |
| 12 | #include <arch_helpers.h> |
| 13 | #include <common/bl_common.h> |
| 14 | #include <common/debug.h> |
| 15 | #include <common/desc_image_load.h> |
| 16 | #include <drivers/generic_delay_timer.h> |
Louis Mayencourt | 81bd916 | 2019-10-17 15:14:25 +0100 | [diff] [blame] | 17 | #include <lib/fconf/fconf.h> |
Manish V Badarkhe | 99a8e14 | 2020-06-11 22:32:11 +0100 | [diff] [blame] | 18 | #include <lib/fconf/fconf_dyn_cfg_getter.h> |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 19 | #ifdef SPD_opteed |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 20 | #include <lib/optee_utils.h> |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 21 | #endif |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 22 | #include <lib/utils.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 23 | #include <plat/arm/common/plat_arm.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 24 | #include <plat/common/platform.h> |
| 25 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 26 | /* Data structure which holds the extents of the trusted SRAM for BL2 */ |
| 27 | static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); |
| 28 | |
Soby Mathew | c44110d | 2018-02-20 12:50:47 +0000 | [diff] [blame] | 29 | /* |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 30 | * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 31 | * for `meminfo_t` data structure and fw_configs passed from BL1. |
Soby Mathew | c44110d | 2018-02-20 12:50:47 +0000 | [diff] [blame] | 32 | */ |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 33 | CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); |
Soby Mathew | c44110d | 2018-02-20 12:50:47 +0000 | [diff] [blame] | 34 | |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 35 | /* Weak definitions may be overridden in specific ARM standard platform */ |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 36 | #pragma weak bl2_early_platform_setup2 |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 37 | #pragma weak bl2_platform_setup |
| 38 | #pragma weak bl2_plat_arch_setup |
| 39 | #pragma weak bl2_plat_sec_mem_layout |
| 40 | |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 41 | #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ |
| 42 | bl2_tzram_layout.total_base, \ |
| 43 | bl2_tzram_layout.total_size, \ |
| 44 | MT_MEMORY | MT_RW | MT_SECURE) |
| 45 | |
Dimitris Papastamos | 9576baa | 2018-06-08 13:17:26 +0100 | [diff] [blame] | 46 | |
Daniel Boulby | 07d2687 | 2018-06-27 16:45:48 +0100 | [diff] [blame] | 47 | #pragma weak arm_bl2_plat_handle_post_image_load |
Dimitris Papastamos | 9576baa | 2018-06-08 13:17:26 +0100 | [diff] [blame] | 48 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 49 | /******************************************************************************* |
| 50 | * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 |
| 51 | * in x0. This memory layout is sitting at the base of the free trusted SRAM. |
| 52 | * Copy it to a safe location before its reclaimed by later BL2 functionality. |
| 53 | ******************************************************************************/ |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 54 | void arm_bl2_early_platform_setup(uintptr_t fw_config, |
Sandrine Bailleux | b3b6e22 | 2018-07-11 12:44:22 +0200 | [diff] [blame] | 55 | struct meminfo *mem_layout) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 56 | { |
Manish V Badarkhe | 99a8e14 | 2020-06-11 22:32:11 +0100 | [diff] [blame] | 57 | const struct dyn_cfg_dtb_info_t *tb_fw_config_info; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 58 | /* Initialize the console to provide early debug support */ |
Antonio Nino Diaz | 23ede6a | 2018-06-19 09:29:36 +0100 | [diff] [blame] | 59 | arm_console_boot_init(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 60 | |
| 61 | /* Setup the BL2 memory layout */ |
| 62 | bl2_tzram_layout = *mem_layout; |
| 63 | |
Louis Mayencourt | 81bd916 | 2019-10-17 15:14:25 +0100 | [diff] [blame] | 64 | /* Fill the properties struct with the info from the config dtb */ |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 65 | if (fw_config != 0U) { |
Manish V Badarkhe | 99a8e14 | 2020-06-11 22:32:11 +0100 | [diff] [blame] | 66 | fconf_populate("FW_CONFIG", fw_config); |
| 67 | } |
| 68 | |
| 69 | /* TB_FW_CONFIG was also loaded by BL1 */ |
| 70 | tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); |
| 71 | if (tb_fw_config_info != NULL) { |
| 72 | fconf_populate("TB_FW", tb_fw_config_info->config_addr); |
Louis Mayencourt | 81bd916 | 2019-10-17 15:14:25 +0100 | [diff] [blame] | 73 | } |
| 74 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 75 | /* Initialise the IO layer and register platform IO devices */ |
| 76 | plat_arm_io_setup(); |
| 77 | } |
| 78 | |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 79 | void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 80 | { |
Soby Mathew | 96a1c6b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 81 | arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); |
| 82 | |
Soby Mathew | 1ced6b8 | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 83 | generic_delay_timer_init(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | /* |
Soby Mathew | 45e39e2 | 2018-03-26 15:16:46 +0100 | [diff] [blame] | 87 | * Perform BL2 preload setup. Currently we initialise the dynamic |
| 88 | * configuration here. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 89 | */ |
Soby Mathew | 45e39e2 | 2018-03-26 15:16:46 +0100 | [diff] [blame] | 90 | void bl2_plat_preload_setup(void) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 91 | { |
Soby Mathew | 96a1c6b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 92 | arm_bl2_dyn_cfg_init(); |
Soby Mathew | 45e39e2 | 2018-03-26 15:16:46 +0100 | [diff] [blame] | 93 | } |
Soby Mathew | 96a1c6b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 94 | |
Soby Mathew | 45e39e2 | 2018-03-26 15:16:46 +0100 | [diff] [blame] | 95 | /* |
| 96 | * Perform ARM standard platform setup. |
| 97 | */ |
| 98 | void arm_bl2_platform_setup(void) |
| 99 | { |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 100 | /* Initialize the secure environment */ |
| 101 | plat_arm_security_setup(); |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 102 | |
| 103 | #if defined(PLAT_ARM_MEM_PROT_ADDR) |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 104 | arm_nor_psci_do_static_mem_protect(); |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 105 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | void bl2_platform_setup(void) |
| 109 | { |
| 110 | arm_bl2_platform_setup(); |
| 111 | } |
| 112 | |
| 113 | /******************************************************************************* |
| 114 | * Perform the very early platform specific architectural setup here. At the |
| 115 | * moment this is only initializes the mmu in a quick and dirty way. |
| 116 | ******************************************************************************/ |
| 117 | void arm_bl2_plat_arch_setup(void) |
| 118 | { |
Soby Mathew | b985648 | 2018-09-18 11:42:42 +0100 | [diff] [blame] | 119 | #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG |
| 120 | /* |
| 121 | * Ensure ARM platforms don't use coherent memory in BL2 unless |
| 122 | * cryptocell integration is enabled. |
| 123 | */ |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 124 | assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 125 | #endif |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 126 | |
| 127 | const mmap_region_t bl_regions[] = { |
| 128 | MAP_BL2_TOTAL, |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 129 | ARM_MAP_BL_RO, |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 130 | #if USE_ROMLIB |
| 131 | ARM_MAP_ROMLIB_CODE, |
| 132 | ARM_MAP_ROMLIB_DATA, |
| 133 | #endif |
Soby Mathew | b985648 | 2018-09-18 11:42:42 +0100 | [diff] [blame] | 134 | #if ARM_CRYPTOCELL_INTEG |
| 135 | ARM_MAP_BL_COHERENT_RAM, |
| 136 | #endif |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 137 | {0} |
| 138 | }; |
| 139 | |
Roberto Vargas | 344ff02 | 2018-10-19 16:44:18 +0100 | [diff] [blame] | 140 | setup_page_tables(bl_regions, plat_arm_get_mmap()); |
Yatharth Kochar | a5f77d3 | 2016-07-04 11:26:14 +0100 | [diff] [blame] | 141 | |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 142 | #ifdef __aarch64__ |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 143 | enable_mmu_el1(0); |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 144 | #else |
| 145 | enable_mmu_svc_mon(0); |
Yatharth Kochar | a5f77d3 | 2016-07-04 11:26:14 +0100 | [diff] [blame] | 146 | #endif |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 147 | |
| 148 | arm_setup_romlib(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | void bl2_plat_arch_setup(void) |
| 152 | { |
| 153 | arm_bl2_plat_arch_setup(); |
| 154 | } |
| 155 | |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 156 | int arm_bl2_handle_post_image_load(unsigned int image_id) |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 157 | { |
| 158 | int err = 0; |
| 159 | bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 160 | #ifdef SPD_opteed |
| 161 | bl_mem_params_node_t *pager_mem_params = NULL; |
| 162 | bl_mem_params_node_t *paged_mem_params = NULL; |
| 163 | #endif |
Zelalem | e8dadb1 | 2020-02-05 14:12:39 -0600 | [diff] [blame] | 164 | assert(bl_mem_params != NULL); |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 165 | |
| 166 | switch (image_id) { |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 167 | #ifdef __aarch64__ |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 168 | case BL32_IMAGE_ID: |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 169 | #ifdef SPD_opteed |
| 170 | pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); |
| 171 | assert(pager_mem_params); |
| 172 | |
| 173 | paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); |
| 174 | assert(paged_mem_params); |
| 175 | |
| 176 | err = parse_optee_header(&bl_mem_params->ep_info, |
| 177 | &pager_mem_params->image_info, |
| 178 | &paged_mem_params->image_info); |
| 179 | if (err != 0) { |
| 180 | WARN("OPTEE header parse error.\n"); |
| 181 | } |
| 182 | #endif |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 183 | bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); |
| 184 | break; |
Yatharth Kochar | a5f77d3 | 2016-07-04 11:26:14 +0100 | [diff] [blame] | 185 | #endif |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 186 | |
| 187 | case BL33_IMAGE_ID: |
| 188 | /* BL33 expects to receive the primary CPU MPID (through r0) */ |
| 189 | bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); |
| 190 | bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); |
| 191 | break; |
| 192 | |
| 193 | #ifdef SCP_BL2_BASE |
| 194 | case SCP_BL2_IMAGE_ID: |
| 195 | /* The subsequent handling of SCP_BL2 is platform specific */ |
| 196 | err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); |
| 197 | if (err) { |
| 198 | WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); |
| 199 | } |
| 200 | break; |
| 201 | #endif |
Jonathan Wright | ff957ed | 2018-03-14 15:24:00 +0000 | [diff] [blame] | 202 | default: |
| 203 | /* Do nothing in default case */ |
| 204 | break; |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 205 | } |
| 206 | |
| 207 | return err; |
| 208 | } |
| 209 | |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 210 | /******************************************************************************* |
| 211 | * This function can be used by the platforms to update/use image |
| 212 | * information for given `image_id`. |
| 213 | ******************************************************************************/ |
Daniel Boulby | 07d2687 | 2018-06-27 16:45:48 +0100 | [diff] [blame] | 214 | int arm_bl2_plat_handle_post_image_load(unsigned int image_id) |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 215 | { |
Olivier Deprez | 042db53 | 2020-03-19 09:27:11 +0100 | [diff] [blame] | 216 | #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 |
Manish Pandey | 1fa6ecb | 2020-02-25 11:38:19 +0000 | [diff] [blame] | 217 | /* For Secure Partitions we don't need post processing */ |
| 218 | if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && |
| 219 | (image_id < MAX_NUMBER_IDS)) { |
| 220 | return 0; |
| 221 | } |
| 222 | #endif |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 223 | return arm_bl2_handle_post_image_load(image_id); |
| 224 | } |
| 225 | |
Daniel Boulby | 07d2687 | 2018-06-27 16:45:48 +0100 | [diff] [blame] | 226 | int bl2_plat_handle_post_image_load(unsigned int image_id) |
| 227 | { |
| 228 | return arm_bl2_plat_handle_post_image_load(image_id); |
| 229 | } |