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Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01001/*
Zelalem Aweke688fbf72021-07-09 11:37:10 -05002 * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef EL3_COMMON_MACROS_S
8#define EL3_COMMON_MACROS_S
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01009
10#include <arch.h>
11#include <asm_macros.S>
Manish V Badarkhee07e8082020-07-23 12:43:25 +010012#include <context.h>
Varun Wadekar5dc9e9c2020-05-16 20:59:30 -070013#include <lib/xlat_tables/xlat_tables_defs.h>
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010014
15 /*
16 * Helper macro to initialise EL3 registers we care about.
17 */
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000018 .macro el3_arch_init_common
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010019 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010020 * SCTLR_EL3 has already been initialised - read current value before
21 * modifying.
22 *
23 * SCTLR_EL3.I: Enable the instruction cache.
24 *
Qixiang Xu3cc39172018-03-05 09:31:11 +080025 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault
David Cunadofee86532017-04-13 22:38:29 +010026 * exception is generated if a load or store instruction executed at
27 * EL3 uses the SP as the base address and the SP is not aligned to a
28 * 16-byte boundary.
29 *
30 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that
31 * load or store one or more registers have an alignment check that the
32 * address being accessed is aligned to the size of the data element(s)
33 * being accessed.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010034 * ---------------------------------------------------------------------
35 */
36 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
37 mrs x0, sctlr_el3
38 orr x0, x0, x1
39 msr sctlr_el3, x0
40 isb
41
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090042#ifdef IMAGE_BL31
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010043 /* ---------------------------------------------------------------------
44 * Initialise the per-cpu cache pointer to the CPU.
45 * This is done early to enable crash reporting to have access to crash
46 * stack. Since crash reporting depends on cpu_data to report the
47 * unhandled exception, not doing so can lead to recursive exceptions
48 * due to a NULL TPIDR_EL3.
49 * ---------------------------------------------------------------------
50 */
51 bl init_cpu_data_ptr
52#endif /* IMAGE_BL31 */
53
54 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010055 * Initialise SCR_EL3, setting all fields rather than relying on hw.
56 * All fields are architecturally UNKNOWN on reset. The following fields
57 * do not change during the TF lifetime. The remaining fields are set to
58 * zero here but are updated ahead of transitioning to a lower EL in the
59 * function cm_init_context_common().
60 *
61 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
62 * EL2, EL1 and EL0 are not trapped to EL3.
63 *
64 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
65 * EL2, EL1 and EL0 are not trapped to EL3.
66 *
67 * SCR_EL3.SIF: Set to one to disable instruction fetches from
68 * Non-secure memory.
69 *
70 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
71 * both Security states and both Execution states.
72 *
73 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
74 * to EL3 when executing at any EL.
Jeenu Viswambharancbad6612018-08-15 14:29:29 +010075 *
76 * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature,
77 * disable traps to EL3 when accessing key registers or using pointer
78 * authentication instructions from lower ELs.
Gerald Lejeune632d6df2016-03-22 09:29:23 +010079 * ---------------------------------------------------------------------
80 */
Antonio Nino Diaz594811b2019-01-31 11:58:00 +000081 mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \
David Cunadofee86532017-04-13 22:38:29 +010082 & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT))
Antonio Nino Diaz594811b2019-01-31 11:58:00 +000083#if CTX_INCLUDE_PAUTH_REGS
84 /*
85 * If the pointer authentication registers are saved during world
86 * switches, enable pointer authentication everywhere, as it is safe to
87 * do so.
88 */
89 orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT)
90#endif
Zelalem Aweke688fbf72021-07-09 11:37:10 -050091#if ENABLE_RME
92 /*
93 * TODO: Settting the EEL2 bit to allow EL3 access to secure only registers
94 * in context management. This will need to be refactored.
95 */
96 orr x0, x0, #SCR_EEL2_BIT
97#endif
Gerald Lejeune632d6df2016-03-22 09:29:23 +010098 msr scr_el3, x0
David Cunado5f55e282016-10-31 17:37:34 +000099
100 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100101 * Initialise MDCR_EL3, setting all fields rather than relying on hw.
102 * Some fields are architecturally UNKNOWN on reset.
103 *
104 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
105 * Debug exceptions, other than Breakpoint Instruction exceptions, are
106 * disabled from all ELs in Secure state.
107 *
108 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
109 * privileged debug from S-EL1.
110 *
111 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
112 * access to the powerdown debug registers do not trap to EL3.
113 *
114 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
115 * debug registers, other than those registers that are controlled by
116 * MDCR_EL3.TDOSA.
117 *
118 * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
119 * accesses to all Performance Monitors registers do not trap to EL3.
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000120 *
121 * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is
122 * prohibited in Secure state. This bit is RES0 in versions of the
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100123 * architecture with FEAT_PMUv3p5 not implemented, setting it to 1
124 * doesn't have any effect on them.
125 *
126 * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is
127 * prohibited in EL3. This bit is RES0 in versions of the
128 * architecture with FEAT_PMUv3p7 not implemented, setting it to 1
129 * doesn't have any effect on them.
Petre-Ionut Tudoradd24a42019-10-03 17:09:08 +0100130 *
131 * MDCR_EL3.SPME: Set to zero so that event counting by the programmable
132 * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2
133 * Debug is not implemented this bit does not have any effect on the
134 * counters unless there is support for the implementation defined
135 * authentication interface ExternalSecureNoninvasiveDebugEnabled().
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100136 *
137 * MDCR_EL3.NSTB, MDCR_EL3.NSTBE: Set to zero so that Trace Buffer
138 * owning security state is Secure state. If FEAT_TRBE is implemented,
139 * accesses to Trace Buffer control registers at EL2 and EL1 in any
140 * security state generates trap exceptions to EL3.
141 * If FEAT_TRBE is not implemented, these bits are RES0.
Manish V Badarkhe8ce33942021-07-18 02:26:27 +0100142 *
143 * MDCR_EL3.TTRF: Set to one so that access to trace filter control
144 * registers in non-monitor mode generate EL3 trap exception,
145 * unless the access generates a higher priority exception when trace
146 * filter control(FEAT_TRF) is implemented.
147 * When FEAT_TRF is not implemented, this bit is RES0.
David Cunado5f55e282016-10-31 17:37:34 +0000148 * ---------------------------------------------------------------------
149 */
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000150 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100151 MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \
152 MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100153 MDCR_TDA_BIT | MDCR_TPM_BIT | MDCR_NSTB(MDCR_NSTB_EL1) | \
Manish V Badarkhe8ce33942021-07-18 02:26:27 +0100154 MDCR_NSTBE | MDCR_TTRF_BIT))
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000155
Manish V Badarkhe8ce33942021-07-18 02:26:27 +0100156 mrs x1, id_aa64dfr0_el1
157 ubfx x1, x1, #ID_AA64DFR0_TRACEFILT_SHIFT, #ID_AA64DFR0_TRACEFILT_LENGTH
158 cbz x1, 1f
159 orr x0, x0, #MDCR_TTRF_BIT
1601:
dp-arm595d0d52017-02-08 11:51:50 +0000161 msr mdcr_el3, x0
David Cunado5f55e282016-10-31 17:37:34 +0000162
Gerald Lejeune632d6df2016-03-22 09:29:23 +0100163 /* ---------------------------------------------------------------------
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100164 * Initialise PMCR_EL0 setting all fields rather than relying
165 * on hw. Some fields are architecturally UNKNOWN on reset.
166 *
167 * PMCR_EL0.LP: Set to one so that event counter overflow, that
168 * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment
169 * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU
170 * is implemented. This bit is RES0 in versions of the architecture
171 * earlier than ARMv8.5, setting it to 1 doesn't have any effect
172 * on them.
173 *
174 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that
175 * is recorded in PMOVSCLR_EL0[31], occurs on the increment
176 * that changes PMCCNTR_EL0[63] from 1 to 0.
177 *
178 * PMCR_EL0.DP: Set to one so that the cycle counter,
179 * PMCCNTR_EL0 does not count when event counting is prohibited.
180 *
181 * PMCR_EL0.X: Set to zero to disable export of events.
182 *
183 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0
184 * counts on every clock cycle.
185 * ---------------------------------------------------------------------
186 */
187 mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \
188 PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \
189 ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT))
190
191 msr pmcr_el0, x0
192
193 /* ---------------------------------------------------------------------
Gerald Lejeune632d6df2016-03-22 09:29:23 +0100194 * Enable External Aborts and SError Interrupts now that the exception
195 * vectors have been setup.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100196 * ---------------------------------------------------------------------
197 */
198 msr daifclr, #DAIF_ABT_BIT
199
200 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100201 * Initialise CPTR_EL3, setting all fields rather than relying on hw.
202 * All fields are architecturally UNKNOWN on reset.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100203 *
David Cunadofee86532017-04-13 22:38:29 +0100204 * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1,
205 * CPTR_EL2, CPACR, or HCPTR do not trap to EL3.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100206 *
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100207 * CPTR_EL3.TTA: Set to one so that accesses to the trace system
208 * registers trap to EL3 from all exception levels and security
209 * states when system register trace is implemented.
210 * When system register trace is not implemented, this bit is RES0 and
211 * hence set to zero.
212 *
David Cunadofee86532017-04-13 22:38:29 +0100213 * CPTR_EL3.TTA: Set to zero so that System register accesses to the
214 * trace registers do not trap to EL3.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100215 *
David Cunadoce88eee2017-10-20 11:30:57 +0100216 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
217 * by Advanced SIMD, floating-point or SVE instructions (if implemented)
218 * do not trap to EL3.
Max Shvetsovc4502772021-03-22 11:59:37 +0000219 *
220 * CPTR_EL3.TAM: Set to one so that Activity Monitor access is
221 * trapped to EL3 by default.
222 *
223 * CPTR_EL3.EZ: Set to zero so that all SVE functionality is trapped
224 * to EL3 by default.
johpow019baade32021-07-08 14:14:00 -0500225 *
226 * CPTR_EL3.ESM: Set to zero so that all SME functionality is trapped
227 * to EL3 by default.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100228 */
Max Shvetsovc4502772021-03-22 11:59:37 +0000229
David Cunadofee86532017-04-13 22:38:29 +0100230 mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT))
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100231 mrs x1, id_aa64dfr0_el1
232 ubfx x1, x1, #ID_AA64DFR0_TRACEVER_SHIFT, #ID_AA64DFR0_TRACEVER_LENGTH
233 cbz x1, 1f
234 orr x0, x0, #TTA_BIT
2351:
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100236 msr cptr_el3, x0
Sathees Balya0911df12018-12-06 13:33:24 +0000237
238 /*
239 * If Data Independent Timing (DIT) functionality is implemented,
240 * always enable DIT in EL3
241 */
242 mrs x0, id_aa64pfr0_el1
243 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
244 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
245 bne 1f
246 mov x0, #DIT_BIT
247 msr DIT, x0
2481:
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100249 .endm
250
251/* -----------------------------------------------------------------------------
252 * This is the super set of actions that need to be performed during a cold boot
Juan Castillo7d199412015-12-14 09:35:25 +0000253 * or a warm boot in EL3. This code is shared by BL1 and BL31.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100254 *
255 * This macro will always perform reset handling, architectural initialisations
256 * and stack setup. The rest of the actions are optional because they might not
257 * be needed, depending on the context in which this macro is called. This is
258 * why this macro is parameterised ; each parameter allows to enable/disable
259 * some actions.
260 *
David Cunadofee86532017-04-13 22:38:29 +0100261 * _init_sctlr:
262 * Whether the macro needs to initialise SCTLR_EL3, including configuring
263 * the endianness of data accesses.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100264 *
265 * _warm_boot_mailbox:
266 * Whether the macro needs to detect the type of boot (cold/warm). The
267 * detection is based on the platform entrypoint address : if it is zero
268 * then it is a cold boot, otherwise it is a warm boot. In the latter case,
269 * this macro jumps on the platform entrypoint address.
270 *
271 * _secondary_cold_boot:
272 * Whether the macro needs to identify the CPU that is calling it: primary
273 * CPU or secondary CPU. The primary CPU will be allowed to carry on with
274 * the platform initialisations, while the secondaries will be put in a
275 * platform-specific state in the meantime.
276 *
277 * If the caller knows this macro will only be called by the primary CPU
278 * then this parameter can be defined to 0 to skip this step.
279 *
280 * _init_memory:
281 * Whether the macro needs to initialise the memory.
282 *
283 * _init_c_runtime:
284 * Whether the macro needs to initialise the C runtime environment.
285 *
286 * _exception_vectors:
287 * Address of the exception vectors to program in the VBAR_EL3 register.
Manish Pandeyc8257682019-11-26 11:34:17 +0000288 *
289 * _pie_fixup_size:
290 * Size of memory region to fixup Global Descriptor Table (GDT).
291 *
292 * A non-zero value is expected when firmware needs GDT to be fixed-up.
293 *
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100294 * -----------------------------------------------------------------------------
295 */
296 .macro el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100297 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
Manish Pandeyc8257682019-11-26 11:34:17 +0000298 _init_memory, _init_c_runtime, _exception_vectors, \
299 _pie_fixup_size
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100300
David Cunadofee86532017-04-13 22:38:29 +0100301 .if \_init_sctlr
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100302 /* -------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100303 * This is the initialisation of SCTLR_EL3 and so must ensure
304 * that all fields are explicitly set rather than relying on hw.
305 * Some fields reset to an IMPLEMENTATION DEFINED value and
306 * others are architecturally UNKNOWN on reset.
307 *
308 * SCTLR.EE: Set the CPU endianness before doing anything that
309 * might involve memory reads or writes. Set to zero to select
310 * Little Endian.
311 *
312 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can
313 * force all memory regions that are writeable to be treated as
314 * XN (Execute-never). Set to zero so that this control has no
315 * effect on memory access permissions.
316 *
Qixiang Xu3cc39172018-03-05 09:31:11 +0800317 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
David Cunadofee86532017-04-13 22:38:29 +0100318 *
319 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000320 *
321 * SCTLR.DSSBS: Set to zero to disable speculation store bypass
322 * safe behaviour upon exception entry to EL3.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100323 * -------------------------------------------------------------
324 */
David Cunadofee86532017-04-13 22:38:29 +0100325 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000326 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT))
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100327 msr sctlr_el3, x0
328 isb
David Cunadofee86532017-04-13 22:38:29 +0100329 .endif /* _init_sctlr */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100330
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000331#if DISABLE_MTPMU
332 bl mtpmu_disable
333#endif
334
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100335 .if \_warm_boot_mailbox
336 /* -------------------------------------------------------------
337 * This code will be executed for both warm and cold resets.
338 * Now is the time to distinguish between the two.
339 * Query the platform entrypoint address and if it is not zero
340 * then it means it is a warm boot so jump to this address.
341 * -------------------------------------------------------------
342 */
Soby Mathew3700a922015-07-13 11:21:11 +0100343 bl plat_get_my_entrypoint
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100344 cbz x0, do_cold_boot
345 br x0
346
347 do_cold_boot:
348 .endif /* _warm_boot_mailbox */
349
Manish Pandeyc8257682019-11-26 11:34:17 +0000350 .if \_pie_fixup_size
351#if ENABLE_PIE
352 /*
353 * ------------------------------------------------------------
354 * If PIE is enabled fixup the Global descriptor Table only
355 * once during primary core cold boot path.
356 *
357 * Compile time base address, required for fixup, is calculated
358 * using "pie_fixup" label present within first page.
359 * ------------------------------------------------------------
360 */
361 pie_fixup:
362 ldr x0, =pie_fixup
Jimmy Brissoned202072020-08-04 16:18:52 -0500363 and x0, x0, #~(PAGE_SIZE_MASK)
Manish Pandeyc8257682019-11-26 11:34:17 +0000364 mov_imm x1, \_pie_fixup_size
365 add x1, x1, x0
366 bl fixup_gdt_reloc
367#endif /* ENABLE_PIE */
368 .endif /* _pie_fixup_size */
369
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000370 /* ---------------------------------------------------------------------
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000371 * Set the exception vectors.
372 * ---------------------------------------------------------------------
373 */
374 adr x0, \_exception_vectors
375 msr vbar_el3, x0
376 isb
377
Zelalem Aweke688fbf72021-07-09 11:37:10 -0500378#if !(defined(IMAGE_BL2) && ENABLE_RME)
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000379 /* ---------------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000380 * It is a cold boot.
381 * Perform any processor specific actions upon reset e.g. cache, TLB
382 * invalidations etc.
383 * ---------------------------------------------------------------------
384 */
385 bl reset_handler
Zelalem Aweke688fbf72021-07-09 11:37:10 -0500386#endif
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000387
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000388 el3_arch_init_common
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000389
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100390 .if \_secondary_cold_boot
391 /* -------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000392 * Check if this is a primary or secondary CPU cold boot.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100393 * The primary CPU will set up the platform while the
394 * secondaries are placed in a platform-specific state until the
395 * primary CPU performs the necessary actions to bring them out
396 * of that state and allows entry into the OS.
397 * -------------------------------------------------------------
398 */
Soby Mathew3700a922015-07-13 11:21:11 +0100399 bl plat_is_my_cpu_primary
Soby Matheweb3bbf12015-06-08 12:32:50 +0100400 cbnz w0, do_primary_cold_boot
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100401
402 /* This is a cold boot on a secondary CPU */
403 bl plat_secondary_cold_boot_setup
404 /* plat_secondary_cold_boot_setup() is not supposed to return */
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000405 bl el3_panic
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100406
407 do_primary_cold_boot:
408 .endif /* _secondary_cold_boot */
409
410 /* ---------------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000411 * Initialize memory now. Secondary CPU initialization won't get to this
412 * point.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100413 * ---------------------------------------------------------------------
414 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100415
416 .if \_init_memory
417 bl platform_mem_init
418 .endif /* _init_memory */
419
420 /* ---------------------------------------------------------------------
421 * Init C runtime environment:
422 * - Zero-initialise the NOBITS sections. There are 2 of them:
423 * - the .bss section;
424 * - the coherent memory section (if any).
425 * - Relocate the data section from ROM to RAM, if required.
426 * ---------------------------------------------------------------------
427 */
428 .if \_init_c_runtime
Zelalem Aweke688fbf72021-07-09 11:37:10 -0500429#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \
430 ((BL2_AT_EL3 && BL2_INV_DCACHE) || ENABLE_RME))
Achin Guptae9c4a642015-09-11 16:03:13 +0100431 /* -------------------------------------------------------------
432 * Invalidate the RW memory used by the BL31 image. This
433 * includes the data and NOBITS sections. This is done to
434 * safeguard against possible corruption of this memory by
435 * dirty cache lines in a system cache as a result of use by
Zelalem Awekeb0d69e82021-10-15 17:25:52 -0500436 * an earlier boot loader stage. If PIE is enabled however,
437 * RO sections including the GOT may be modified during
438 * pie fixup. Therefore, to be on the safe side, invalidate
439 * the entire image region if PIE is enabled.
Achin Guptae9c4a642015-09-11 16:03:13 +0100440 * -------------------------------------------------------------
441 */
Zelalem Awekeb0d69e82021-10-15 17:25:52 -0500442#if ENABLE_PIE
443#if SEPARATE_CODE_AND_RODATA
444 adrp x0, __TEXT_START__
445 add x0, x0, :lo12:__TEXT_START__
446#else
447 adrp x0, __RO_START__
448 add x0, x0, :lo12:__RO_START__
449#endif /* SEPARATE_CODE_AND_RODATA */
450#else
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100451 adrp x0, __RW_START__
452 add x0, x0, :lo12:__RW_START__
Zelalem Awekeb0d69e82021-10-15 17:25:52 -0500453#endif /* ENABLE_PIE */
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100454 adrp x1, __RW_END__
455 add x1, x1, :lo12:__RW_END__
Achin Guptae9c4a642015-09-11 16:03:13 +0100456 sub x1, x1, x0
457 bl inv_dcache_range
Samuel Holland31a14e12018-10-17 21:40:18 -0500458#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION
459 adrp x0, __NOBITS_START__
460 add x0, x0, :lo12:__NOBITS_START__
461 adrp x1, __NOBITS_END__
462 add x1, x1, :lo12:__NOBITS_END__
463 sub x1, x1, x0
464 bl inv_dcache_range
465#endif
Roberto Vargase0e99462017-10-30 14:43:43 +0000466#endif
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100467 adrp x0, __BSS_START__
468 add x0, x0, :lo12:__BSS_START__
Achin Guptae9c4a642015-09-11 16:03:13 +0100469
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100470 adrp x1, __BSS_END__
471 add x1, x1, :lo12:__BSS_END__
472 sub x1, x1, x0
Douglas Raillard21362a92016-12-02 13:51:54 +0000473 bl zeromem
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100474
475#if USE_COHERENT_MEM
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100476 adrp x0, __COHERENT_RAM_START__
477 add x0, x0, :lo12:__COHERENT_RAM_START__
478 adrp x1, __COHERENT_RAM_END_UNALIGNED__
479 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__
480 sub x1, x1, x0
Douglas Raillard21362a92016-12-02 13:51:54 +0000481 bl zeromem
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100482#endif
483
Lionel Debieved2f21b82019-05-27 09:32:00 +0200484#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM)
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100485 adrp x0, __DATA_RAM_START__
486 add x0, x0, :lo12:__DATA_RAM_START__
487 adrp x1, __DATA_ROM_START__
488 add x1, x1, :lo12:__DATA_ROM_START__
489 adrp x2, __DATA_RAM_END__
490 add x2, x2, :lo12:__DATA_RAM_END__
491 sub x2, x2, x0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100492 bl memcpy16
493#endif
494 .endif /* _init_c_runtime */
495
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100496 /* ---------------------------------------------------------------------
497 * Use SP_EL0 for the C runtime stack.
498 * ---------------------------------------------------------------------
499 */
500 msr spsel, #0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100501
502 /* ---------------------------------------------------------------------
503 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
504 * the MMU is enabled. There is no risk of reading stale stack memory
505 * after enabling the MMU as only the primary CPU is running at the
506 * moment.
507 * ---------------------------------------------------------------------
508 */
Soby Mathew3700a922015-07-13 11:21:11 +0100509 bl plat_set_my_stack
Douglas Raillard306593d2017-02-24 18:14:15 +0000510
511#if STACK_PROTECTOR_ENABLED
512 .if \_init_c_runtime
513 bl update_stack_protector_canary
514 .endif /* _init_c_runtime */
515#endif
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100516 .endm
517
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100518 .macro apply_at_speculative_wa
519#if ERRATA_SPECULATIVE_AT
520 /*
521 * Explicitly save x30 so as to free up a register and to enable
522 * branching and also, save x29 which will be used in the called
523 * function
524 */
525 stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
526 bl save_and_update_ptw_el1_sys_regs
527 ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
528#endif
529 .endm
530
531 .macro restore_ptw_el1_sys_regs
532#if ERRATA_SPECULATIVE_AT
533 /* -----------------------------------------------------------
534 * In case of ERRATA_SPECULATIVE_AT, must follow below order
535 * to ensure that page table walk is not enabled until
536 * restoration of all EL1 system registers. TCR_EL1 register
537 * should be updated at the end which restores previous page
538 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB
539 * ensures that CPU does below steps in order.
540 *
541 * 1. Ensure all other system registers are written before
542 * updating SCTLR_EL1 using ISB.
543 * 2. Restore SCTLR_EL1 register.
544 * 3. Ensure SCTLR_EL1 written successfully using ISB.
545 * 4. Restore TCR_EL1 register.
546 * -----------------------------------------------------------
547 */
548 isb
549 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1]
550 msr sctlr_el1, x28
551 isb
552 msr tcr_el1, x29
553#endif
554 .endm
555
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000556#endif /* EL3_COMMON_MACROS_S */