blob: 1dff69035b122ee86628199d3973e3d1f51a09c0 [file] [log] [blame]
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <common/debug.h>
8#include <lib/mmio.h>
9
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020010#include "rcar_def.h"
11#include "cpg_registers.h"
12#include "rcar_private.h"
13
14static void bl2_secure_cpg_init(void);
15
16#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
17static void bl2_realtime_cpg_init_h3(void);
18static void bl2_system_cpg_init_h3(void);
19#endif
20
21#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
22static void bl2_realtime_cpg_init_m3(void);
23static void bl2_system_cpg_init_m3(void);
24#endif
25
26#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
27static void bl2_realtime_cpg_init_m3n(void);
28static void bl2_system_cpg_init_m3n(void);
29#endif
30
Marek Vasut2b9b0fc2019-01-05 13:57:16 +010031#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020032static void bl2_realtime_cpg_init_e3(void);
33static void bl2_system_cpg_init_e3(void);
34#endif
35
36typedef struct {
37 uintptr_t adr;
38 uint32_t val;
39} reg_setting_t;
40
41static void bl2_secure_cpg_init(void)
42{
43 uint32_t stop_cr2, reset_cr2;
44
45#if (RCAR_LSI == RCAR_E3)
ldts0a596b42018-11-06 10:17:12 +010046 reset_cr2 = 0x10000000U;
47 stop_cr2 = 0xEFFFFFFFU;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020048#else
49 reset_cr2 = 0x14000000U;
50 stop_cr2 = 0xEBFFFFFFU;
51#endif
52 /** Secure Module Stop Control Registers */
53 cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
54 cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
55 cpg_write(SCMSTPCR2, stop_cr2);
56 cpg_write(SCMSTPCR3, 0xFFFFFFFFU);
57 cpg_write(SCMSTPCR4, 0x7FFFFFFFU);
58 cpg_write(SCMSTPCR5, 0xBFFFFFFFU);
59 cpg_write(SCMSTPCR6, 0xFFFFFFFFU);
60 cpg_write(SCMSTPCR7, 0xFFFFFFFFU);
61 cpg_write(SCMSTPCR8, 0xFFFFFFFFU);
62 cpg_write(SCMSTPCR9, 0xFFFDFFFFU);
63 cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
64 cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
65
66 /** Secure Software Reset Access Enable Control Registers */
67 cpg_write(SCSRSTECR0, 0x00000000U);
68 cpg_write(SCSRSTECR1, 0x00000000U);
69 cpg_write(SCSRSTECR2, reset_cr2);
70 cpg_write(SCSRSTECR3, 0x00000000U);
71 cpg_write(SCSRSTECR4, 0x80000003U);
72 cpg_write(SCSRSTECR5, 0x40000000U);
73 cpg_write(SCSRSTECR6, 0x00000000U);
74 cpg_write(SCSRSTECR7, 0x00000000U);
75 cpg_write(SCSRSTECR8, 0x00000000U);
76 cpg_write(SCSRSTECR9, 0x00020000U);
77 cpg_write(SCSRSTECR10, 0x00000000U);
78 cpg_write(SCSRSTECR11, 0x00000000U);
79}
80
81#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
82static void bl2_realtime_cpg_init_h3(void)
83{
84 uint32_t cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
85 uint32_t cr0, cr8;
86
87 cr0 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
88 0x00200000U : 0x00210000U;
89 cr8 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
90 0x01F1FFF4U : 0x01F1FFF7U;
91
92 cpg_write(RMSTPCR0, cr0);
93 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
94 cpg_write(RMSTPCR2, 0x040E0FDCU);
95 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
96 cpg_write(RMSTPCR4, 0x80000004U);
97 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
98 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
99 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
100 cpg_write(RMSTPCR8, cr8);
101 cpg_write(RMSTPCR9, 0xFFFFFFFEU);
102 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
103 cpg_write(RMSTPCR11, 0x000000B7U);
104}
105
106static void bl2_system_cpg_init_h3(void)
107{
108 /** System Module Stop Control Registers */
109 cpg_write(SMSTPCR0, 0x00210000U);
110 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
111 cpg_write(SMSTPCR2, 0x040E2FDCU);
112 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
113 cpg_write(SMSTPCR4, 0x80000004U);
114 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
115 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
116 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
117 cpg_write(SMSTPCR8, 0x01F1FFF5U);
118 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
119 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
120 cpg_write(SMSTPCR11, 0x000000B7U);
121}
122#endif
123
124#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
125static void bl2_realtime_cpg_init_m3(void)
126{
127 /** Realtime Module Stop Control Registers */
128 cpg_write(RMSTPCR0, 0x00200000U);
129 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
130 cpg_write(RMSTPCR2, 0x040E0FDCU);
131 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
132 cpg_write(RMSTPCR4, 0x80000004U);
133 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
134 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
135 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
136 cpg_write(RMSTPCR8, 0x01F1FFF7U);
137 cpg_write(RMSTPCR9, 0xFFFFFFFEU);
138 cpg_write(RMSTPCR10, 0xFFFEFFE0U);
139 cpg_write(RMSTPCR11, 0x000000B7U);
140}
141
142static void bl2_system_cpg_init_m3(void)
143{
144 /** System Module Stop Control Registers */
145 cpg_write(SMSTPCR0, 0x00200000U);
146 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
147 cpg_write(SMSTPCR2, 0x040E2FDCU);
148 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
149 cpg_write(SMSTPCR4, 0x80000004U);
150 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
151 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
152 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
153 cpg_write(SMSTPCR8, 0x01F1FFF7U);
154 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
155 cpg_write(SMSTPCR10, 0xFFFEFFE0U);
156 cpg_write(SMSTPCR11, 0x000000B7U);
157}
158#endif
159
160#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
161static void bl2_realtime_cpg_init_m3n(void)
162{
163 /** Realtime Module Stop Control Registers */
164 cpg_write(RMSTPCR0, 0x00210000U);
165 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
166 cpg_write(RMSTPCR2, 0x040E0FDCU);
167 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
168 cpg_write(RMSTPCR4, 0x80000004U);
169 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
170 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
171 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
172 cpg_write(RMSTPCR8, 0x00F1FFF7U);
173 cpg_write(RMSTPCR9, 0xFFFFFFFFU);
174 cpg_write(RMSTPCR10, 0xFFFFFFE0U);
175 cpg_write(RMSTPCR11, 0x000000B7U);
176}
177
178static void bl2_system_cpg_init_m3n(void)
179{
180 /* System Module Stop Control Registers */
181 cpg_write(SMSTPCR0, 0x00210000U);
182 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
183 cpg_write(SMSTPCR2, 0x040E2FDCU);
184 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
185 cpg_write(SMSTPCR4, 0x80000004U);
186 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
187 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
188 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
189 cpg_write(SMSTPCR8, 0x00F1FFF7U);
190 cpg_write(SMSTPCR9, 0xFFFFFFFFU);
191 cpg_write(SMSTPCR10, 0xFFFFFFE0U);
192 cpg_write(SMSTPCR11, 0x000000B7U);
193}
194#endif
195
Marek Vasut2b9b0fc2019-01-05 13:57:16 +0100196#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200197static void bl2_realtime_cpg_init_e3(void)
198{
199 /* Realtime Module Stop Control Registers */
200 cpg_write(RMSTPCR0, 0x00210000U);
201 cpg_write(RMSTPCR1, 0xFFFFFFFFU);
202 cpg_write(RMSTPCR2, 0x000E0FDCU);
203 cpg_write(RMSTPCR3, 0xFFFFFFDFU);
204 cpg_write(RMSTPCR4, 0x80000004U);
205 cpg_write(RMSTPCR5, 0xC3FFFFFFU);
206 cpg_write(RMSTPCR6, 0xFFFFFFFFU);
207 cpg_write(RMSTPCR7, 0xFFFFFFFFU);
208 cpg_write(RMSTPCR8, 0x00F1FFF7U);
209 cpg_write(RMSTPCR9, 0xFFFFFFDFU);
210 cpg_write(RMSTPCR10, 0xFFFFFFE8U);
211 cpg_write(RMSTPCR11, 0x000000B7U);
212}
213
214static void bl2_system_cpg_init_e3(void)
215{
216 /* System Module Stop Control Registers */
217 cpg_write(SMSTPCR0, 0x00210000U);
218 cpg_write(SMSTPCR1, 0xFFFFFFFFU);
219 cpg_write(SMSTPCR2, 0x000E2FDCU);
220 cpg_write(SMSTPCR3, 0xFFFFFBDFU);
221 cpg_write(SMSTPCR4, 0x80000004U);
222 cpg_write(SMSTPCR5, 0xC3FFFFFFU);
223 cpg_write(SMSTPCR6, 0xFFFFFFFFU);
224 cpg_write(SMSTPCR7, 0xFFFFFFFFU);
225 cpg_write(SMSTPCR8, 0x00F1FFF7U);
226 cpg_write(SMSTPCR9, 0xFFFFFFDFU);
227 cpg_write(SMSTPCR10, 0xFFFFFFE8U);
228 cpg_write(SMSTPCR11, 0x000000B7U);
229}
230#endif
231
232void bl2_cpg_init(void)
233{
234 uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK;
235#if RCAR_LSI == RCAR_AUTO
236 uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
237#endif
238 bl2_secure_cpg_init();
239
240 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
241 boot_cpu == MODEMR_BOOT_CPU_CA53) {
242#if RCAR_LSI == RCAR_AUTO
243
244 switch (product) {
245 case RCAR_PRODUCT_H3:
246 bl2_realtime_cpg_init_h3();
247 break;
248 case RCAR_PRODUCT_M3:
249 bl2_realtime_cpg_init_m3();
250 break;
251 case RCAR_PRODUCT_M3N:
252 bl2_realtime_cpg_init_m3n();
253 break;
Marek Vasut2b9b0fc2019-01-05 13:57:16 +0100254 case RCAR_PRODUCT_E3:
255 bl2_realtime_cpg_init_e3();
256 break;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200257 default:
258 panic();
259 break;
260 }
261#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
262 bl2_realtime_cpg_init_h3();
263#elif RCAR_LSI == RCAR_M3
264 bl2_realtime_cpg_init_m3();
265#elif RCAR_LSI == RCAR_M3N
266 bl2_realtime_cpg_init_m3n();
267#elif RCAR_LSI == RCAR_E3
268 bl2_realtime_cpg_init_e3();
269#else
270#error "Don't have CPG initialize routine(unknown)."
271#endif
272 }
273}
274
275void bl2_system_cpg_init(void)
276{
277#if RCAR_LSI == RCAR_AUTO
278 uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
279
280 switch (product) {
281 case RCAR_PRODUCT_H3:
282 bl2_system_cpg_init_h3();
283 break;
284 case RCAR_PRODUCT_M3:
285 bl2_system_cpg_init_m3();
286 break;
287 case RCAR_PRODUCT_M3N:
288 bl2_system_cpg_init_m3n();
289 break;
Marek Vasut2b9b0fc2019-01-05 13:57:16 +0100290 case RCAR_PRODUCT_E3:
291 bl2_system_cpg_init_e3();
292 break;
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200293 default:
294 panic();
295 break;
296 }
297#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
298 bl2_system_cpg_init_h3();
299#elif RCAR_LSI == RCAR_M3
300 bl2_system_cpg_init_m3();
301#elif RCAR_LSI == RCAR_M3N
302 bl2_system_cpg_init_m3n();
303#elif RCAR_LSI == RCAR_E3
304 bl2_system_cpg_init_e3();
305#else
306#error "Don't have CPG initialize routine(unknown)."
307#endif
308}