Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Louis Mayencourt | 81bd916 | 2019-10-17 15:14:25 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <string.h> |
| 9 | |
| 10 | #include <platform_def.h> |
| 11 | |
| 12 | #include <arch_helpers.h> |
| 13 | #include <common/bl_common.h> |
| 14 | #include <common/debug.h> |
| 15 | #include <common/desc_image_load.h> |
| 16 | #include <drivers/generic_delay_timer.h> |
Louis Mayencourt | 81bd916 | 2019-10-17 15:14:25 +0100 | [diff] [blame] | 17 | #include <lib/fconf/fconf.h> |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 18 | #ifdef SPD_opteed |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 19 | #include <lib/optee_utils.h> |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 20 | #endif |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 21 | #include <lib/utils.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 22 | #include <plat/arm/common/plat_arm.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 23 | #include <plat/common/platform.h> |
| 24 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 25 | /* Data structure which holds the extents of the trusted SRAM for BL2 */ |
| 26 | static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); |
| 27 | |
Soby Mathew | c44110d | 2018-02-20 12:50:47 +0000 | [diff] [blame] | 28 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 29 | * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is |
| 30 | * for `meminfo_t` data structure and fw_configs passed from BL1. |
Soby Mathew | c44110d | 2018-02-20 12:50:47 +0000 | [diff] [blame] | 31 | */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 32 | CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows); |
Soby Mathew | c44110d | 2018-02-20 12:50:47 +0000 | [diff] [blame] | 33 | |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 34 | /* Weak definitions may be overridden in specific ARM standard platform */ |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 35 | #pragma weak bl2_early_platform_setup2 |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 36 | #pragma weak bl2_platform_setup |
| 37 | #pragma weak bl2_plat_arch_setup |
| 38 | #pragma weak bl2_plat_sec_mem_layout |
| 39 | |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 40 | #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ |
| 41 | bl2_tzram_layout.total_base, \ |
| 42 | bl2_tzram_layout.total_size, \ |
| 43 | MT_MEMORY | MT_RW | MT_SECURE) |
| 44 | |
Dimitris Papastamos | 9576baa | 2018-06-08 13:17:26 +0100 | [diff] [blame] | 45 | |
Daniel Boulby | 07d2687 | 2018-06-27 16:45:48 +0100 | [diff] [blame] | 46 | #pragma weak arm_bl2_plat_handle_post_image_load |
Dimitris Papastamos | 9576baa | 2018-06-08 13:17:26 +0100 | [diff] [blame] | 47 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 48 | /******************************************************************************* |
| 49 | * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 |
| 50 | * in x0. This memory layout is sitting at the base of the free trusted SRAM. |
| 51 | * Copy it to a safe location before its reclaimed by later BL2 functionality. |
| 52 | ******************************************************************************/ |
Sandrine Bailleux | b3b6e22 | 2018-07-11 12:44:22 +0200 | [diff] [blame] | 53 | void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, |
| 54 | struct meminfo *mem_layout) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 55 | { |
| 56 | /* Initialize the console to provide early debug support */ |
Antonio Nino Diaz | 23ede6a | 2018-06-19 09:29:36 +0100 | [diff] [blame] | 57 | arm_console_boot_init(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 58 | |
| 59 | /* Setup the BL2 memory layout */ |
| 60 | bl2_tzram_layout = *mem_layout; |
| 61 | |
Louis Mayencourt | 81bd916 | 2019-10-17 15:14:25 +0100 | [diff] [blame] | 62 | /* Fill the properties struct with the info from the config dtb */ |
| 63 | if (tb_fw_config != 0U) { |
| 64 | fconf_populate(tb_fw_config); |
| 65 | } |
| 66 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 67 | /* Initialise the IO layer and register platform IO devices */ |
| 68 | plat_arm_io_setup(); |
| 69 | } |
| 70 | |
Soby Mathew | 7d5a2e7 | 2018-01-10 15:59:31 +0000 | [diff] [blame] | 71 | void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 72 | { |
Soby Mathew | 96a1c6b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 73 | arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); |
| 74 | |
Soby Mathew | 1ced6b8 | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 75 | generic_delay_timer_init(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | /* |
Soby Mathew | 45e39e2 | 2018-03-26 15:16:46 +0100 | [diff] [blame] | 79 | * Perform BL2 preload setup. Currently we initialise the dynamic |
| 80 | * configuration here. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 81 | */ |
Soby Mathew | 45e39e2 | 2018-03-26 15:16:46 +0100 | [diff] [blame] | 82 | void bl2_plat_preload_setup(void) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 83 | { |
Soby Mathew | 96a1c6b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 84 | arm_bl2_dyn_cfg_init(); |
Soby Mathew | 45e39e2 | 2018-03-26 15:16:46 +0100 | [diff] [blame] | 85 | } |
Soby Mathew | 96a1c6b | 2018-01-15 14:45:33 +0000 | [diff] [blame] | 86 | |
Soby Mathew | 45e39e2 | 2018-03-26 15:16:46 +0100 | [diff] [blame] | 87 | /* |
| 88 | * Perform ARM standard platform setup. |
| 89 | */ |
| 90 | void arm_bl2_platform_setup(void) |
| 91 | { |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 92 | /* Initialize the secure environment */ |
| 93 | plat_arm_security_setup(); |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 94 | |
| 95 | #if defined(PLAT_ARM_MEM_PROT_ADDR) |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 96 | arm_nor_psci_do_static_mem_protect(); |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 97 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | void bl2_platform_setup(void) |
| 101 | { |
| 102 | arm_bl2_platform_setup(); |
| 103 | } |
| 104 | |
| 105 | /******************************************************************************* |
| 106 | * Perform the very early platform specific architectural setup here. At the |
| 107 | * moment this is only initializes the mmu in a quick and dirty way. |
| 108 | ******************************************************************************/ |
| 109 | void arm_bl2_plat_arch_setup(void) |
| 110 | { |
Soby Mathew | b985648 | 2018-09-18 11:42:42 +0100 | [diff] [blame] | 111 | #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG |
| 112 | /* |
| 113 | * Ensure ARM platforms don't use coherent memory in BL2 unless |
| 114 | * cryptocell integration is enabled. |
| 115 | */ |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 116 | assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 117 | #endif |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 118 | |
| 119 | const mmap_region_t bl_regions[] = { |
| 120 | MAP_BL2_TOTAL, |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 121 | ARM_MAP_BL_RO, |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 122 | #if USE_ROMLIB |
| 123 | ARM_MAP_ROMLIB_CODE, |
| 124 | ARM_MAP_ROMLIB_DATA, |
| 125 | #endif |
Soby Mathew | b985648 | 2018-09-18 11:42:42 +0100 | [diff] [blame] | 126 | #if ARM_CRYPTOCELL_INTEG |
| 127 | ARM_MAP_BL_COHERENT_RAM, |
| 128 | #endif |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 129 | {0} |
| 130 | }; |
| 131 | |
Roberto Vargas | 344ff02 | 2018-10-19 16:44:18 +0100 | [diff] [blame] | 132 | setup_page_tables(bl_regions, plat_arm_get_mmap()); |
Yatharth Kochar | a5f77d3 | 2016-07-04 11:26:14 +0100 | [diff] [blame] | 133 | |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 134 | #ifdef __aarch64__ |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 135 | enable_mmu_el1(0); |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 136 | #else |
| 137 | enable_mmu_svc_mon(0); |
Yatharth Kochar | a5f77d3 | 2016-07-04 11:26:14 +0100 | [diff] [blame] | 138 | #endif |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 139 | |
| 140 | arm_setup_romlib(); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | void bl2_plat_arch_setup(void) |
| 144 | { |
| 145 | arm_bl2_plat_arch_setup(); |
| 146 | } |
| 147 | |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 148 | int arm_bl2_handle_post_image_load(unsigned int image_id) |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 149 | { |
| 150 | int err = 0; |
| 151 | bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 152 | #ifdef SPD_opteed |
| 153 | bl_mem_params_node_t *pager_mem_params = NULL; |
| 154 | bl_mem_params_node_t *paged_mem_params = NULL; |
| 155 | #endif |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 156 | assert(bl_mem_params); |
| 157 | |
| 158 | switch (image_id) { |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 159 | #ifdef __aarch64__ |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 160 | case BL32_IMAGE_ID: |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 161 | #ifdef SPD_opteed |
| 162 | pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); |
| 163 | assert(pager_mem_params); |
| 164 | |
| 165 | paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); |
| 166 | assert(paged_mem_params); |
| 167 | |
| 168 | err = parse_optee_header(&bl_mem_params->ep_info, |
| 169 | &pager_mem_params->image_info, |
| 170 | &paged_mem_params->image_info); |
| 171 | if (err != 0) { |
| 172 | WARN("OPTEE header parse error.\n"); |
| 173 | } |
| 174 | #endif |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 175 | bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); |
| 176 | break; |
Yatharth Kochar | a5f77d3 | 2016-07-04 11:26:14 +0100 | [diff] [blame] | 177 | #endif |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 178 | |
| 179 | case BL33_IMAGE_ID: |
| 180 | /* BL33 expects to receive the primary CPU MPID (through r0) */ |
| 181 | bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); |
| 182 | bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); |
| 183 | break; |
| 184 | |
| 185 | #ifdef SCP_BL2_BASE |
| 186 | case SCP_BL2_IMAGE_ID: |
| 187 | /* The subsequent handling of SCP_BL2 is platform specific */ |
| 188 | err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); |
| 189 | if (err) { |
| 190 | WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); |
| 191 | } |
| 192 | break; |
| 193 | #endif |
Jonathan Wright | ff957ed | 2018-03-14 15:24:00 +0000 | [diff] [blame] | 194 | default: |
| 195 | /* Do nothing in default case */ |
| 196 | break; |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 197 | } |
| 198 | |
| 199 | return err; |
| 200 | } |
| 201 | |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 202 | /******************************************************************************* |
| 203 | * This function can be used by the platforms to update/use image |
| 204 | * information for given `image_id`. |
| 205 | ******************************************************************************/ |
Daniel Boulby | 07d2687 | 2018-06-27 16:45:48 +0100 | [diff] [blame] | 206 | int arm_bl2_plat_handle_post_image_load(unsigned int image_id) |
Yatharth Kochar | ede39cb | 2016-11-14 12:01:04 +0000 | [diff] [blame] | 207 | { |
| 208 | return arm_bl2_handle_post_image_load(image_id); |
| 209 | } |
| 210 | |
Daniel Boulby | 07d2687 | 2018-06-27 16:45:48 +0100 | [diff] [blame] | 211 | int bl2_plat_handle_post_image_load(unsigned int image_id) |
| 212 | { |
| 213 | return arm_bl2_plat_handle_post_image_load(image_id); |
| 214 | } |