Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | #include <assert.h> |
| 9 | #include <bakery_lock.h> |
| 10 | #include <debug.h> |
| 11 | #include <delay_timer.h> |
Derek Basehore | e13bc54 | 2017-02-24 14:31:36 +0800 | [diff] [blame] | 12 | #include <dfs.h> |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 13 | #include <errno.h> |
Caesar Wang | a5dc64d | 2016-05-25 19:04:47 +0800 | [diff] [blame] | 14 | #include <gpio.h> |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 15 | #include <mmio.h> |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 16 | #include <m0_ctl.h> |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 17 | #include <platform.h> |
| 18 | #include <platform_def.h> |
Caesar Wang | a5dc64d | 2016-05-25 19:04:47 +0800 | [diff] [blame] | 19 | #include <plat_params.h> |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 20 | #include <plat_private.h> |
| 21 | #include <rk3399_def.h> |
Xing Zheng | 22a9871 | 2017-02-24 14:56:41 +0800 | [diff] [blame] | 22 | #include <secure.h> |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 23 | #include <soc.h> |
| 24 | #include <pmu.h> |
| 25 | #include <pmu_com.h> |
Caesar Wang | ed6b9a5 | 2016-08-11 02:11:45 +0800 | [diff] [blame] | 26 | #include <pwm.h> |
Caesar Wang | e67b1de | 2016-08-17 17:22:10 -0700 | [diff] [blame] | 27 | #include <bl31.h> |
Caesar Wang | 5339d18 | 2016-10-27 01:13:34 +0800 | [diff] [blame] | 28 | #include <suspend.h> |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 29 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 30 | DEFINE_BAKERY_LOCK(rockchip_pd_lock); |
| 31 | |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 32 | static uint32_t cpu_warm_boot_addr; |
| 33 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 34 | /* |
| 35 | * There are two ways to powering on or off on core. |
| 36 | * 1) Control it power domain into on or off in PMU_PWRDN_CON reg, |
| 37 | * it is core_pwr_pd mode |
| 38 | * 2) Enable the core power manage in PMU_CORE_PM_CON reg, |
| 39 | * then, if the core enter into wfi, it power domain will be |
| 40 | * powered off automatically. it is core_pwr_wfi or core_pwr_wfi_int mode |
| 41 | * so we need core_pm_cfg_info to distinguish which method be used now. |
| 42 | */ |
| 43 | |
| 44 | static uint32_t core_pm_cfg_info[PLATFORM_CORE_COUNT] |
| 45 | #if USE_COHERENT_MEM |
| 46 | __attribute__ ((section("tzfw_coherent_mem"))) |
| 47 | #endif |
| 48 | ;/* coheront */ |
| 49 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 50 | static void pmu_bus_idle_req(uint32_t bus, uint32_t state) |
| 51 | { |
| 52 | uint32_t bus_id = BIT(bus); |
| 53 | uint32_t bus_req; |
| 54 | uint32_t wait_cnt = 0; |
| 55 | uint32_t bus_state, bus_ack; |
| 56 | |
| 57 | if (state) |
| 58 | bus_req = BIT(bus); |
| 59 | else |
| 60 | bus_req = 0; |
| 61 | |
| 62 | mmio_clrsetbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, bus_id, bus_req); |
| 63 | |
| 64 | do { |
| 65 | bus_state = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & bus_id; |
| 66 | bus_ack = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK) & bus_id; |
| 67 | wait_cnt++; |
| 68 | } while ((bus_state != bus_req || bus_ack != bus_req) && |
| 69 | (wait_cnt < MAX_WAIT_COUNT)); |
| 70 | |
| 71 | if (bus_state != bus_req || bus_ack != bus_req) { |
| 72 | INFO("%s:st=%x(%x)\n", __func__, |
| 73 | mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), |
| 74 | bus_state); |
| 75 | INFO("%s:st=%x(%x)\n", __func__, |
| 76 | mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK), |
| 77 | bus_ack); |
| 78 | } |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 79 | } |
| 80 | |
| 81 | struct pmu_slpdata_s pmu_slpdata; |
| 82 | |
| 83 | static void qos_save(void) |
| 84 | { |
| 85 | if (pmu_power_domain_st(PD_GPU) == pmu_pd_on) |
| 86 | RESTORE_QOS(pmu_slpdata.gpu_qos, GPU); |
| 87 | if (pmu_power_domain_st(PD_ISP0) == pmu_pd_on) { |
| 88 | RESTORE_QOS(pmu_slpdata.isp0_m0_qos, ISP0_M0); |
| 89 | RESTORE_QOS(pmu_slpdata.isp0_m1_qos, ISP0_M1); |
| 90 | } |
| 91 | if (pmu_power_domain_st(PD_ISP1) == pmu_pd_on) { |
| 92 | RESTORE_QOS(pmu_slpdata.isp1_m0_qos, ISP1_M0); |
| 93 | RESTORE_QOS(pmu_slpdata.isp1_m1_qos, ISP1_M1); |
| 94 | } |
| 95 | if (pmu_power_domain_st(PD_VO) == pmu_pd_on) { |
| 96 | RESTORE_QOS(pmu_slpdata.vop_big_r, VOP_BIG_R); |
| 97 | RESTORE_QOS(pmu_slpdata.vop_big_w, VOP_BIG_W); |
| 98 | RESTORE_QOS(pmu_slpdata.vop_little, VOP_LITTLE); |
| 99 | } |
| 100 | if (pmu_power_domain_st(PD_HDCP) == pmu_pd_on) |
| 101 | RESTORE_QOS(pmu_slpdata.hdcp_qos, HDCP); |
| 102 | if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on) |
| 103 | RESTORE_QOS(pmu_slpdata.gmac_qos, GMAC); |
| 104 | if (pmu_power_domain_st(PD_CCI) == pmu_pd_on) { |
| 105 | RESTORE_QOS(pmu_slpdata.cci_m0_qos, CCI_M0); |
| 106 | RESTORE_QOS(pmu_slpdata.cci_m1_qos, CCI_M1); |
| 107 | } |
| 108 | if (pmu_power_domain_st(PD_SD) == pmu_pd_on) |
| 109 | RESTORE_QOS(pmu_slpdata.sdmmc_qos, SDMMC); |
| 110 | if (pmu_power_domain_st(PD_EMMC) == pmu_pd_on) |
| 111 | RESTORE_QOS(pmu_slpdata.emmc_qos, EMMC); |
| 112 | if (pmu_power_domain_st(PD_SDIOAUDIO) == pmu_pd_on) |
| 113 | RESTORE_QOS(pmu_slpdata.sdio_qos, SDIO); |
| 114 | if (pmu_power_domain_st(PD_GIC) == pmu_pd_on) |
| 115 | RESTORE_QOS(pmu_slpdata.gic_qos, GIC); |
| 116 | if (pmu_power_domain_st(PD_RGA) == pmu_pd_on) { |
| 117 | RESTORE_QOS(pmu_slpdata.rga_r_qos, RGA_R); |
| 118 | RESTORE_QOS(pmu_slpdata.rga_w_qos, RGA_W); |
| 119 | } |
| 120 | if (pmu_power_domain_st(PD_IEP) == pmu_pd_on) |
| 121 | RESTORE_QOS(pmu_slpdata.iep_qos, IEP); |
| 122 | if (pmu_power_domain_st(PD_USB3) == pmu_pd_on) { |
| 123 | RESTORE_QOS(pmu_slpdata.usb_otg0_qos, USB_OTG0); |
| 124 | RESTORE_QOS(pmu_slpdata.usb_otg1_qos, USB_OTG1); |
| 125 | } |
| 126 | if (pmu_power_domain_st(PD_PERIHP) == pmu_pd_on) { |
| 127 | RESTORE_QOS(pmu_slpdata.usb_host0_qos, USB_HOST0); |
| 128 | RESTORE_QOS(pmu_slpdata.usb_host1_qos, USB_HOST1); |
| 129 | RESTORE_QOS(pmu_slpdata.perihp_nsp_qos, PERIHP_NSP); |
| 130 | } |
| 131 | if (pmu_power_domain_st(PD_PERILP) == pmu_pd_on) { |
| 132 | RESTORE_QOS(pmu_slpdata.dmac0_qos, DMAC0); |
| 133 | RESTORE_QOS(pmu_slpdata.dmac1_qos, DMAC1); |
| 134 | RESTORE_QOS(pmu_slpdata.dcf_qos, DCF); |
| 135 | RESTORE_QOS(pmu_slpdata.crypto0_qos, CRYPTO0); |
| 136 | RESTORE_QOS(pmu_slpdata.crypto1_qos, CRYPTO1); |
| 137 | RESTORE_QOS(pmu_slpdata.perilp_nsp_qos, PERILP_NSP); |
| 138 | RESTORE_QOS(pmu_slpdata.perilpslv_nsp_qos, PERILPSLV_NSP); |
| 139 | RESTORE_QOS(pmu_slpdata.peri_cm1_qos, PERI_CM1); |
| 140 | } |
| 141 | if (pmu_power_domain_st(PD_VDU) == pmu_pd_on) |
| 142 | RESTORE_QOS(pmu_slpdata.video_m0_qos, VIDEO_M0); |
| 143 | if (pmu_power_domain_st(PD_VCODEC) == pmu_pd_on) { |
| 144 | RESTORE_QOS(pmu_slpdata.video_m1_r_qos, VIDEO_M1_R); |
| 145 | RESTORE_QOS(pmu_slpdata.video_m1_w_qos, VIDEO_M1_W); |
| 146 | } |
| 147 | } |
| 148 | |
| 149 | static void qos_restore(void) |
| 150 | { |
| 151 | if (pmu_power_domain_st(PD_GPU) == pmu_pd_on) |
| 152 | SAVE_QOS(pmu_slpdata.gpu_qos, GPU); |
| 153 | if (pmu_power_domain_st(PD_ISP0) == pmu_pd_on) { |
| 154 | SAVE_QOS(pmu_slpdata.isp0_m0_qos, ISP0_M0); |
| 155 | SAVE_QOS(pmu_slpdata.isp0_m1_qos, ISP0_M1); |
| 156 | } |
| 157 | if (pmu_power_domain_st(PD_ISP1) == pmu_pd_on) { |
| 158 | SAVE_QOS(pmu_slpdata.isp1_m0_qos, ISP1_M0); |
| 159 | SAVE_QOS(pmu_slpdata.isp1_m1_qos, ISP1_M1); |
| 160 | } |
| 161 | if (pmu_power_domain_st(PD_VO) == pmu_pd_on) { |
| 162 | SAVE_QOS(pmu_slpdata.vop_big_r, VOP_BIG_R); |
| 163 | SAVE_QOS(pmu_slpdata.vop_big_w, VOP_BIG_W); |
| 164 | SAVE_QOS(pmu_slpdata.vop_little, VOP_LITTLE); |
| 165 | } |
| 166 | if (pmu_power_domain_st(PD_HDCP) == pmu_pd_on) |
| 167 | SAVE_QOS(pmu_slpdata.hdcp_qos, HDCP); |
| 168 | if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on) |
| 169 | SAVE_QOS(pmu_slpdata.gmac_qos, GMAC); |
| 170 | if (pmu_power_domain_st(PD_CCI) == pmu_pd_on) { |
| 171 | SAVE_QOS(pmu_slpdata.cci_m0_qos, CCI_M0); |
| 172 | SAVE_QOS(pmu_slpdata.cci_m1_qos, CCI_M1); |
| 173 | } |
| 174 | if (pmu_power_domain_st(PD_SD) == pmu_pd_on) |
| 175 | SAVE_QOS(pmu_slpdata.sdmmc_qos, SDMMC); |
| 176 | if (pmu_power_domain_st(PD_EMMC) == pmu_pd_on) |
| 177 | SAVE_QOS(pmu_slpdata.emmc_qos, EMMC); |
| 178 | if (pmu_power_domain_st(PD_SDIOAUDIO) == pmu_pd_on) |
| 179 | SAVE_QOS(pmu_slpdata.sdio_qos, SDIO); |
| 180 | if (pmu_power_domain_st(PD_GIC) == pmu_pd_on) |
| 181 | SAVE_QOS(pmu_slpdata.gic_qos, GIC); |
| 182 | if (pmu_power_domain_st(PD_RGA) == pmu_pd_on) { |
| 183 | SAVE_QOS(pmu_slpdata.rga_r_qos, RGA_R); |
| 184 | SAVE_QOS(pmu_slpdata.rga_w_qos, RGA_W); |
| 185 | } |
| 186 | if (pmu_power_domain_st(PD_IEP) == pmu_pd_on) |
| 187 | SAVE_QOS(pmu_slpdata.iep_qos, IEP); |
| 188 | if (pmu_power_domain_st(PD_USB3) == pmu_pd_on) { |
| 189 | SAVE_QOS(pmu_slpdata.usb_otg0_qos, USB_OTG0); |
| 190 | SAVE_QOS(pmu_slpdata.usb_otg1_qos, USB_OTG1); |
| 191 | } |
| 192 | if (pmu_power_domain_st(PD_PERIHP) == pmu_pd_on) { |
| 193 | SAVE_QOS(pmu_slpdata.usb_host0_qos, USB_HOST0); |
| 194 | SAVE_QOS(pmu_slpdata.usb_host1_qos, USB_HOST1); |
| 195 | SAVE_QOS(pmu_slpdata.perihp_nsp_qos, PERIHP_NSP); |
| 196 | } |
| 197 | if (pmu_power_domain_st(PD_PERILP) == pmu_pd_on) { |
| 198 | SAVE_QOS(pmu_slpdata.dmac0_qos, DMAC0); |
| 199 | SAVE_QOS(pmu_slpdata.dmac1_qos, DMAC1); |
| 200 | SAVE_QOS(pmu_slpdata.dcf_qos, DCF); |
| 201 | SAVE_QOS(pmu_slpdata.crypto0_qos, CRYPTO0); |
| 202 | SAVE_QOS(pmu_slpdata.crypto1_qos, CRYPTO1); |
| 203 | SAVE_QOS(pmu_slpdata.perilp_nsp_qos, PERILP_NSP); |
| 204 | SAVE_QOS(pmu_slpdata.perilpslv_nsp_qos, PERILPSLV_NSP); |
| 205 | SAVE_QOS(pmu_slpdata.peri_cm1_qos, PERI_CM1); |
| 206 | } |
| 207 | if (pmu_power_domain_st(PD_VDU) == pmu_pd_on) |
| 208 | SAVE_QOS(pmu_slpdata.video_m0_qos, VIDEO_M0); |
| 209 | if (pmu_power_domain_st(PD_VCODEC) == pmu_pd_on) { |
| 210 | SAVE_QOS(pmu_slpdata.video_m1_r_qos, VIDEO_M1_R); |
| 211 | SAVE_QOS(pmu_slpdata.video_m1_w_qos, VIDEO_M1_W); |
| 212 | } |
| 213 | } |
| 214 | |
| 215 | static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) |
| 216 | { |
| 217 | uint32_t state; |
| 218 | |
| 219 | if (pmu_power_domain_st(pd_id) == pd_state) |
| 220 | goto out; |
| 221 | |
| 222 | if (pd_state == pmu_pd_on) |
| 223 | pmu_power_domain_ctr(pd_id, pd_state); |
| 224 | |
| 225 | state = (pd_state == pmu_pd_off) ? BUS_IDLE : BUS_ACTIVE; |
| 226 | |
| 227 | switch (pd_id) { |
| 228 | case PD_GPU: |
| 229 | pmu_bus_idle_req(BUS_ID_GPU, state); |
| 230 | break; |
| 231 | case PD_VIO: |
| 232 | pmu_bus_idle_req(BUS_ID_VIO, state); |
| 233 | break; |
| 234 | case PD_ISP0: |
| 235 | pmu_bus_idle_req(BUS_ID_ISP0, state); |
| 236 | break; |
| 237 | case PD_ISP1: |
| 238 | pmu_bus_idle_req(BUS_ID_ISP1, state); |
| 239 | break; |
| 240 | case PD_VO: |
| 241 | pmu_bus_idle_req(BUS_ID_VOPB, state); |
| 242 | pmu_bus_idle_req(BUS_ID_VOPL, state); |
| 243 | break; |
| 244 | case PD_HDCP: |
| 245 | pmu_bus_idle_req(BUS_ID_HDCP, state); |
| 246 | break; |
| 247 | case PD_TCPD0: |
| 248 | break; |
| 249 | case PD_TCPD1: |
| 250 | break; |
| 251 | case PD_GMAC: |
| 252 | pmu_bus_idle_req(BUS_ID_GMAC, state); |
| 253 | break; |
| 254 | case PD_CCI: |
| 255 | pmu_bus_idle_req(BUS_ID_CCIM0, state); |
| 256 | pmu_bus_idle_req(BUS_ID_CCIM1, state); |
| 257 | break; |
| 258 | case PD_SD: |
| 259 | pmu_bus_idle_req(BUS_ID_SD, state); |
| 260 | break; |
| 261 | case PD_EMMC: |
| 262 | pmu_bus_idle_req(BUS_ID_EMMC, state); |
| 263 | break; |
| 264 | case PD_EDP: |
| 265 | pmu_bus_idle_req(BUS_ID_EDP, state); |
| 266 | break; |
| 267 | case PD_SDIOAUDIO: |
| 268 | pmu_bus_idle_req(BUS_ID_SDIOAUDIO, state); |
| 269 | break; |
| 270 | case PD_GIC: |
| 271 | pmu_bus_idle_req(BUS_ID_GIC, state); |
| 272 | break; |
| 273 | case PD_RGA: |
| 274 | pmu_bus_idle_req(BUS_ID_RGA, state); |
| 275 | break; |
| 276 | case PD_VCODEC: |
| 277 | pmu_bus_idle_req(BUS_ID_VCODEC, state); |
| 278 | break; |
| 279 | case PD_VDU: |
| 280 | pmu_bus_idle_req(BUS_ID_VDU, state); |
| 281 | break; |
| 282 | case PD_IEP: |
| 283 | pmu_bus_idle_req(BUS_ID_IEP, state); |
| 284 | break; |
| 285 | case PD_USB3: |
| 286 | pmu_bus_idle_req(BUS_ID_USB3, state); |
| 287 | break; |
| 288 | case PD_PERIHP: |
| 289 | pmu_bus_idle_req(BUS_ID_PERIHP, state); |
| 290 | break; |
| 291 | default: |
| 292 | break; |
| 293 | } |
| 294 | |
| 295 | if (pd_state == pmu_pd_off) |
| 296 | pmu_power_domain_ctr(pd_id, pd_state); |
| 297 | |
| 298 | out: |
| 299 | return 0; |
| 300 | } |
| 301 | |
| 302 | static uint32_t pmu_powerdomain_state; |
| 303 | |
| 304 | static void pmu_power_domains_suspend(void) |
| 305 | { |
| 306 | clk_gate_con_save(); |
| 307 | clk_gate_con_disable(); |
| 308 | qos_save(); |
| 309 | pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); |
| 310 | pmu_set_power_domain(PD_GPU, pmu_pd_off); |
| 311 | pmu_set_power_domain(PD_TCPD0, pmu_pd_off); |
| 312 | pmu_set_power_domain(PD_TCPD1, pmu_pd_off); |
| 313 | pmu_set_power_domain(PD_VO, pmu_pd_off); |
| 314 | pmu_set_power_domain(PD_ISP0, pmu_pd_off); |
| 315 | pmu_set_power_domain(PD_ISP1, pmu_pd_off); |
| 316 | pmu_set_power_domain(PD_HDCP, pmu_pd_off); |
| 317 | pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_off); |
| 318 | pmu_set_power_domain(PD_GMAC, pmu_pd_off); |
| 319 | pmu_set_power_domain(PD_EDP, pmu_pd_off); |
| 320 | pmu_set_power_domain(PD_IEP, pmu_pd_off); |
| 321 | pmu_set_power_domain(PD_RGA, pmu_pd_off); |
| 322 | pmu_set_power_domain(PD_VCODEC, pmu_pd_off); |
| 323 | pmu_set_power_domain(PD_VDU, pmu_pd_off); |
| 324 | clk_gate_con_restore(); |
| 325 | } |
| 326 | |
| 327 | static void pmu_power_domains_resume(void) |
| 328 | { |
| 329 | clk_gate_con_save(); |
| 330 | clk_gate_con_disable(); |
| 331 | if (!(pmu_powerdomain_state & BIT(PD_VDU))) |
| 332 | pmu_set_power_domain(PD_VDU, pmu_pd_on); |
| 333 | if (!(pmu_powerdomain_state & BIT(PD_VCODEC))) |
| 334 | pmu_set_power_domain(PD_VCODEC, pmu_pd_on); |
| 335 | if (!(pmu_powerdomain_state & BIT(PD_RGA))) |
| 336 | pmu_set_power_domain(PD_RGA, pmu_pd_on); |
| 337 | if (!(pmu_powerdomain_state & BIT(PD_IEP))) |
| 338 | pmu_set_power_domain(PD_IEP, pmu_pd_on); |
| 339 | if (!(pmu_powerdomain_state & BIT(PD_EDP))) |
| 340 | pmu_set_power_domain(PD_EDP, pmu_pd_on); |
| 341 | if (!(pmu_powerdomain_state & BIT(PD_GMAC))) |
| 342 | pmu_set_power_domain(PD_GMAC, pmu_pd_on); |
| 343 | if (!(pmu_powerdomain_state & BIT(PD_SDIOAUDIO))) |
| 344 | pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on); |
| 345 | if (!(pmu_powerdomain_state & BIT(PD_HDCP))) |
| 346 | pmu_set_power_domain(PD_HDCP, pmu_pd_on); |
| 347 | if (!(pmu_powerdomain_state & BIT(PD_ISP1))) |
| 348 | pmu_set_power_domain(PD_ISP1, pmu_pd_on); |
| 349 | if (!(pmu_powerdomain_state & BIT(PD_ISP0))) |
| 350 | pmu_set_power_domain(PD_ISP0, pmu_pd_on); |
| 351 | if (!(pmu_powerdomain_state & BIT(PD_VO))) |
| 352 | pmu_set_power_domain(PD_VO, pmu_pd_on); |
| 353 | if (!(pmu_powerdomain_state & BIT(PD_TCPD1))) |
| 354 | pmu_set_power_domain(PD_TCPD1, pmu_pd_on); |
| 355 | if (!(pmu_powerdomain_state & BIT(PD_TCPD0))) |
| 356 | pmu_set_power_domain(PD_TCPD0, pmu_pd_on); |
| 357 | if (!(pmu_powerdomain_state & BIT(PD_GPU))) |
| 358 | pmu_set_power_domain(PD_GPU, pmu_pd_on); |
| 359 | qos_restore(); |
| 360 | clk_gate_con_restore(); |
| 361 | } |
| 362 | |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 363 | void rk3399_flash_l2_b(void) |
| 364 | { |
| 365 | uint32_t wait_cnt = 0; |
| 366 | |
| 367 | mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); |
| 368 | dsb(); |
| 369 | |
| 370 | while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & |
| 371 | BIT(L2_FLUSHDONE_CLUSTER_B))) { |
| 372 | wait_cnt++; |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 373 | if (wait_cnt >= MAX_WAIT_COUNT) |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 374 | WARN("%s:reg %x,wait\n", __func__, |
| 375 | mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); |
| 376 | } |
| 377 | |
| 378 | mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); |
| 379 | } |
| 380 | |
| 381 | static void pmu_scu_b_pwrdn(void) |
| 382 | { |
| 383 | uint32_t wait_cnt = 0; |
| 384 | |
| 385 | if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & |
| 386 | (BIT(PMU_A72_B0_PWRDWN_ST) | BIT(PMU_A72_B1_PWRDWN_ST))) != |
| 387 | (BIT(PMU_A72_B0_PWRDWN_ST) | BIT(PMU_A72_B1_PWRDWN_ST))) { |
| 388 | ERROR("%s: not all cpus is off\n", __func__); |
| 389 | return; |
| 390 | } |
| 391 | |
| 392 | rk3399_flash_l2_b(); |
| 393 | |
| 394 | mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); |
| 395 | |
| 396 | while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & |
| 397 | BIT(STANDBY_BY_WFIL2_CLUSTER_B))) { |
| 398 | wait_cnt++; |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 399 | if (wait_cnt >= MAX_WAIT_COUNT) |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 400 | ERROR("%s:wait cluster-b l2(%x)\n", __func__, |
| 401 | mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); |
| 402 | } |
| 403 | } |
| 404 | |
| 405 | static void pmu_scu_b_pwrup(void) |
| 406 | { |
| 407 | mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); |
| 408 | } |
| 409 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 410 | static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) |
| 411 | { |
Sandrine Bailleux | bd1a374 | 2016-05-05 10:04:15 +0100 | [diff] [blame] | 412 | assert(cpu_id < PLATFORM_CORE_COUNT); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 413 | return core_pm_cfg_info[cpu_id]; |
| 414 | } |
| 415 | |
| 416 | static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value) |
| 417 | { |
Sandrine Bailleux | bd1a374 | 2016-05-05 10:04:15 +0100 | [diff] [blame] | 418 | assert(cpu_id < PLATFORM_CORE_COUNT); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 419 | core_pm_cfg_info[cpu_id] = value; |
| 420 | #if !USE_COHERENT_MEM |
| 421 | flush_dcache_range((uintptr_t)&core_pm_cfg_info[cpu_id], |
| 422 | sizeof(uint32_t)); |
| 423 | #endif |
| 424 | } |
| 425 | |
| 426 | static int cpus_power_domain_on(uint32_t cpu_id) |
| 427 | { |
| 428 | uint32_t cfg_info; |
| 429 | uint32_t cpu_pd = PD_CPUL0 + cpu_id; |
| 430 | /* |
| 431 | * There are two ways to powering on or off on core. |
| 432 | * 1) Control it power domain into on or off in PMU_PWRDN_CON reg |
| 433 | * 2) Enable the core power manage in PMU_CORE_PM_CON reg, |
| 434 | * then, if the core enter into wfi, it power domain will be |
| 435 | * powered off automatically. |
| 436 | */ |
| 437 | |
| 438 | cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id); |
| 439 | |
| 440 | if (cfg_info == core_pwr_pd) { |
| 441 | /* disable core_pm cfg */ |
| 442 | mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), |
| 443 | CORES_PM_DISABLE); |
| 444 | /* if the cores have be on, power off it firstly */ |
| 445 | if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) { |
| 446 | mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 0); |
| 447 | pmu_power_domain_ctr(cpu_pd, pmu_pd_off); |
| 448 | } |
| 449 | |
| 450 | pmu_power_domain_ctr(cpu_pd, pmu_pd_on); |
| 451 | } else { |
| 452 | if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) { |
| 453 | WARN("%s: cpu%d is not in off,!\n", __func__, cpu_id); |
| 454 | return -EINVAL; |
| 455 | } |
| 456 | |
| 457 | mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), |
| 458 | BIT(core_pm_sft_wakeup_en)); |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 459 | dsb(); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 460 | } |
| 461 | |
| 462 | return 0; |
| 463 | } |
| 464 | |
| 465 | static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) |
| 466 | { |
| 467 | uint32_t cpu_pd; |
| 468 | uint32_t core_pm_value; |
| 469 | |
| 470 | cpu_pd = PD_CPUL0 + cpu_id; |
| 471 | if (pmu_power_domain_st(cpu_pd) == pmu_pd_off) |
| 472 | return 0; |
| 473 | |
| 474 | if (pd_cfg == core_pwr_pd) { |
| 475 | if (check_cpu_wfie(cpu_id, CKECK_WFEI_MSK)) |
| 476 | return -EINVAL; |
| 477 | |
| 478 | /* disable core_pm cfg */ |
| 479 | mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), |
| 480 | CORES_PM_DISABLE); |
| 481 | |
| 482 | set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); |
| 483 | pmu_power_domain_ctr(cpu_pd, pmu_pd_off); |
| 484 | } else { |
| 485 | set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); |
| 486 | |
| 487 | core_pm_value = BIT(core_pm_en); |
| 488 | if (pd_cfg == core_pwr_wfi_int) |
| 489 | core_pm_value |= BIT(core_pm_int_wakeup_en); |
| 490 | mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), |
| 491 | core_pm_value); |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 492 | dsb(); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 493 | } |
| 494 | |
| 495 | return 0; |
| 496 | } |
| 497 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 498 | static inline void clst_pwr_domain_suspend(plat_local_state_t lvl_state) |
| 499 | { |
| 500 | uint32_t cpu_id = plat_my_core_pos(); |
| 501 | uint32_t pll_id, clst_st_msk, clst_st_chk_msk, pmu_st; |
| 502 | |
| 503 | assert(cpu_id < PLATFORM_CORE_COUNT); |
| 504 | |
Tony Xie | 6d7d93c | 2016-09-02 11:13:38 -0700 | [diff] [blame] | 505 | if (lvl_state == PLAT_MAX_OFF_STATE) { |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 506 | if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT) { |
| 507 | pll_id = ALPLL_ID; |
| 508 | clst_st_msk = CLST_L_CPUS_MSK; |
| 509 | } else { |
| 510 | pll_id = ABPLL_ID; |
| 511 | clst_st_msk = CLST_B_CPUS_MSK << |
| 512 | PLATFORM_CLUSTER0_CORE_COUNT; |
| 513 | } |
| 514 | |
| 515 | clst_st_chk_msk = clst_st_msk & ~(BIT(cpu_id)); |
| 516 | |
| 517 | pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); |
| 518 | |
| 519 | pmu_st &= clst_st_msk; |
| 520 | |
| 521 | if (pmu_st == clst_st_chk_msk) { |
| 522 | mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), |
| 523 | PLL_SLOW_MODE); |
| 524 | |
| 525 | clst_warmboot_data[pll_id] = PMU_CLST_RET; |
| 526 | |
| 527 | pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); |
| 528 | pmu_st &= clst_st_msk; |
| 529 | if (pmu_st == clst_st_chk_msk) |
| 530 | return; |
| 531 | /* |
| 532 | * it is mean that others cpu is up again, |
| 533 | * we must resume the cfg at once. |
| 534 | */ |
| 535 | mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), |
| 536 | PLL_NOMAL_MODE); |
| 537 | clst_warmboot_data[pll_id] = 0; |
| 538 | } |
| 539 | } |
| 540 | } |
| 541 | |
| 542 | static int clst_pwr_domain_resume(plat_local_state_t lvl_state) |
| 543 | { |
| 544 | uint32_t cpu_id = plat_my_core_pos(); |
| 545 | uint32_t pll_id, pll_st; |
| 546 | |
| 547 | assert(cpu_id < PLATFORM_CORE_COUNT); |
| 548 | |
Tony Xie | 6d7d93c | 2016-09-02 11:13:38 -0700 | [diff] [blame] | 549 | if (lvl_state == PLAT_MAX_OFF_STATE) { |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 550 | if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT) |
| 551 | pll_id = ALPLL_ID; |
| 552 | else |
| 553 | pll_id = ABPLL_ID; |
| 554 | |
| 555 | pll_st = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 3)) >> |
| 556 | PLL_MODE_SHIFT; |
| 557 | |
| 558 | if (pll_st != NORMAL_MODE) { |
| 559 | WARN("%s: clst (%d) is in error mode (%d)\n", |
| 560 | __func__, pll_id, pll_st); |
| 561 | return -1; |
| 562 | } |
| 563 | } |
| 564 | |
| 565 | return 0; |
| 566 | } |
| 567 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 568 | static void nonboot_cpus_off(void) |
| 569 | { |
| 570 | uint32_t boot_cpu, cpu; |
| 571 | |
| 572 | boot_cpu = plat_my_core_pos(); |
| 573 | |
| 574 | /* turn off noboot cpus */ |
| 575 | for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { |
| 576 | if (cpu == boot_cpu) |
| 577 | continue; |
| 578 | cpus_power_domain_off(cpu, core_pwr_pd); |
| 579 | } |
| 580 | } |
| 581 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 582 | int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint) |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 583 | { |
| 584 | uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); |
| 585 | |
Sandrine Bailleux | bd1a374 | 2016-05-05 10:04:15 +0100 | [diff] [blame] | 586 | assert(cpu_id < PLATFORM_CORE_COUNT); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 587 | assert(cpuson_flags[cpu_id] == 0); |
| 588 | cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; |
| 589 | cpuson_entry_point[cpu_id] = entrypoint; |
| 590 | dsb(); |
| 591 | |
| 592 | cpus_power_domain_on(cpu_id); |
| 593 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 594 | return PSCI_E_SUCCESS; |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 595 | } |
| 596 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 597 | int rockchip_soc_cores_pwr_dm_off(void) |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 598 | { |
| 599 | uint32_t cpu_id = plat_my_core_pos(); |
| 600 | |
| 601 | cpus_power_domain_off(cpu_id, core_pwr_wfi); |
| 602 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 603 | return PSCI_E_SUCCESS; |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 604 | } |
| 605 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 606 | int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, |
| 607 | plat_local_state_t lvl_state) |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 608 | { |
| 609 | switch (lvl) { |
| 610 | case MPIDR_AFFLVL1: |
| 611 | clst_pwr_domain_suspend(lvl_state); |
| 612 | break; |
| 613 | default: |
| 614 | break; |
| 615 | } |
| 616 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 617 | return PSCI_E_SUCCESS; |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 618 | } |
| 619 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 620 | int rockchip_soc_cores_pwr_dm_suspend(void) |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 621 | { |
| 622 | uint32_t cpu_id = plat_my_core_pos(); |
| 623 | |
Sandrine Bailleux | bd1a374 | 2016-05-05 10:04:15 +0100 | [diff] [blame] | 624 | assert(cpu_id < PLATFORM_CORE_COUNT); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 625 | assert(cpuson_flags[cpu_id] == 0); |
| 626 | cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 627 | cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint(); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 628 | dsb(); |
| 629 | |
| 630 | cpus_power_domain_off(cpu_id, core_pwr_wfi_int); |
| 631 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 632 | return PSCI_E_SUCCESS; |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 633 | } |
| 634 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 635 | int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state) |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 636 | { |
| 637 | switch (lvl) { |
| 638 | case MPIDR_AFFLVL1: |
| 639 | clst_pwr_domain_suspend(lvl_state); |
| 640 | break; |
| 641 | default: |
| 642 | break; |
| 643 | } |
| 644 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 645 | return PSCI_E_SUCCESS; |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 646 | } |
| 647 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 648 | int rockchip_soc_cores_pwr_dm_on_finish(void) |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 649 | { |
| 650 | uint32_t cpu_id = plat_my_core_pos(); |
| 651 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 652 | mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), |
| 653 | CORES_PM_DISABLE); |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 654 | return PSCI_E_SUCCESS; |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 655 | } |
| 656 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 657 | int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, |
| 658 | plat_local_state_t lvl_state) |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 659 | { |
| 660 | switch (lvl) { |
| 661 | case MPIDR_AFFLVL1: |
| 662 | clst_pwr_domain_resume(lvl_state); |
| 663 | break; |
| 664 | default: |
| 665 | break; |
| 666 | } |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 667 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 668 | return PSCI_E_SUCCESS; |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 669 | } |
| 670 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 671 | int rockchip_soc_cores_pwr_dm_resume(void) |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 672 | { |
| 673 | uint32_t cpu_id = plat_my_core_pos(); |
| 674 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 675 | /* Disable core_pm */ |
| 676 | mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE); |
| 677 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 678 | return PSCI_E_SUCCESS; |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 679 | } |
| 680 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 681 | int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state) |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 682 | { |
| 683 | switch (lvl) { |
| 684 | case MPIDR_AFFLVL1: |
| 685 | clst_pwr_domain_resume(lvl_state); |
| 686 | default: |
| 687 | break; |
| 688 | } |
| 689 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 690 | return PSCI_E_SUCCESS; |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 691 | } |
| 692 | |
Caesar Wang | 34d18d3 | 2016-08-25 06:29:46 +0800 | [diff] [blame] | 693 | /** |
| 694 | * init_pmu_counts - Init timing counts in the PMU register area |
| 695 | * |
| 696 | * At various points when we power up or down parts of the system we need |
| 697 | * a delay to wait for power / clocks to become stable. The PMU has counters |
| 698 | * to help software do the delay properly. Basically, it works like this: |
| 699 | * - Software sets up counter values |
| 700 | * - When software turns on something in the PMU, the counter kicks off |
| 701 | * - The hardware sets a bit automatically when the counter has finished and |
| 702 | * software knows that the initialization is done. |
| 703 | * |
| 704 | * It's software's job to setup these counters. The hardware power on default |
| 705 | * for these settings is conservative, setting everything to 0x5dc0 |
| 706 | * (750 ms in 32 kHz counts or 1 ms in 24 MHz counts). |
| 707 | * |
| 708 | * Note that some of these counters are only really used at suspend/resume |
| 709 | * time (for instance, that's the only time we turn off/on the oscillator) and |
| 710 | * others are used during normal runtime (like turning on/off a CPU or GPU) but |
| 711 | * it doesn't hurt to init everything at boot. |
| 712 | * |
| 713 | * Also note that these counters can run off the 32 kHz clock or the 24 MHz |
| 714 | * clock. While the 24 MHz clock can give us more precision, it's not always |
Caesar Wang | e67b1de | 2016-08-17 17:22:10 -0700 | [diff] [blame] | 715 | * available (like when we turn the oscillator off at sleep time). The |
| 716 | * pmu_use_lf (lf: low freq) is available in power mode. Current understanding |
| 717 | * is that counts work like this: |
Caesar Wang | 34d18d3 | 2016-08-25 06:29:46 +0800 | [diff] [blame] | 718 | * IF (pmu_use_lf == 0) || (power_mode_en == 0) |
| 719 | * use the 24M OSC for counts |
| 720 | * ELSE |
| 721 | * use the 32K OSC for counts |
| 722 | * |
| 723 | * Notes: |
| 724 | * - There is a separate bit for the PMU called PMU_24M_EN_CFG. At the moment |
| 725 | * we always keep that 0. This apparently choose between using the PLL as |
| 726 | * the source for the PMU vs. the 24M clock. If we ever set it to 1 we |
| 727 | * should consider how it affects these counts (if at all). |
| 728 | * - The power_mode_en is documented to auto-clear automatically when we leave |
| 729 | * "power mode". That's why most clocks are on 24M. Only timings used when |
| 730 | * in "power mode" are 32k. |
| 731 | * - In some cases the kernel may override these counts. |
| 732 | * |
| 733 | * The PMU_STABLE_CNT / PMU_OSC_CNT / PMU_PLLLOCK_CNT are important CNTs |
| 734 | * in power mode, we need to ensure that they are available. |
| 735 | */ |
| 736 | static void init_pmu_counts(void) |
| 737 | { |
| 738 | /* COUNTS FOR INSIDE POWER MODE */ |
| 739 | |
| 740 | /* |
| 741 | * From limited testing, need PMU stable >= 2ms, but go overkill |
| 742 | * and choose 30 ms to match testing on past SoCs. Also let |
| 743 | * OSC have 30 ms for stabilization. |
| 744 | */ |
| 745 | mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(30)); |
| 746 | mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(30)); |
| 747 | |
| 748 | /* Unclear what these should be; try 3 ms */ |
| 749 | mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_32K_CNT_MS(3)); |
| 750 | |
| 751 | /* Unclear what this should be, but set the default explicitly */ |
| 752 | mmio_write_32(PMU_BASE + PMU_TIMEOUT_CNT, 0x5dc0); |
| 753 | |
| 754 | /* COUNTS FOR OUTSIDE POWER MODE */ |
| 755 | |
| 756 | /* Put something sorta conservative here until we know better */ |
| 757 | mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(3)); |
| 758 | mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_24M_CNT_MS(1)); |
| 759 | mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_24M_CNT_MS(1)); |
| 760 | mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_24M_CNT_MS(1)); |
| 761 | |
| 762 | /* |
| 763 | * Set CPU/GPU to 1 us. |
| 764 | * |
| 765 | * NOTE: Even though ATF doesn't configure the GPU we'll still setup |
| 766 | * counts here. After all ATF controls all these other bits and also |
| 767 | * chooses which clock these counters use. |
| 768 | */ |
| 769 | mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_US(1)); |
| 770 | mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_US(1)); |
| 771 | mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_US(1)); |
| 772 | mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_US(1)); |
| 773 | mmio_write_32(PMU_BASE + PMU_GPU_PWRDN_CNT, CYCL_24M_CNT_US(1)); |
| 774 | mmio_write_32(PMU_BASE + PMU_GPU_PWRUP_CNT, CYCL_24M_CNT_US(1)); |
| 775 | } |
| 776 | |
Caesar Wang | 5339d18 | 2016-10-27 01:13:34 +0800 | [diff] [blame] | 777 | static uint32_t clk_ddrc_save; |
| 778 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 779 | static void sys_slp_config(void) |
| 780 | { |
| 781 | uint32_t slp_mode_cfg = 0; |
| 782 | |
Caesar Wang | 5339d18 | 2016-10-27 01:13:34 +0800 | [diff] [blame] | 783 | /* keep enabling clk_ddrc_bpll_src_en gate for DDRC */ |
| 784 | clk_ddrc_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(3)); |
| 785 | mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1)); |
| 786 | |
| 787 | prepare_abpll_for_ddrctrl(); |
| 788 | sram_func_set_ddrctl_pll(ABPLL_ID); |
| 789 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 790 | mmio_write_32(GRF_BASE + GRF_SOC_CON4, CCI_FORCE_WAKEUP); |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 791 | mmio_write_32(PMU_BASE + PMU_CCI500_CON, |
| 792 | BIT_WITH_WMSK(PMU_CLR_PREQ_CCI500_HW) | |
| 793 | BIT_WITH_WMSK(PMU_CLR_QREQ_CCI500_HW) | |
| 794 | BIT_WITH_WMSK(PMU_QGATING_CCI500_CFG)); |
| 795 | |
| 796 | mmio_write_32(PMU_BASE + PMU_ADB400_CON, |
| 797 | BIT_WITH_WMSK(PMU_CLR_CORE_L_HW) | |
| 798 | BIT_WITH_WMSK(PMU_CLR_CORE_L_2GIC_HW) | |
| 799 | BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW)); |
| 800 | |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 801 | slp_mode_cfg = BIT(PMU_PWR_MODE_EN) | |
| 802 | BIT(PMU_POWER_OFF_REQ_CFG) | |
| 803 | BIT(PMU_CPU0_PD_EN) | |
| 804 | BIT(PMU_L2_FLUSH_EN) | |
| 805 | BIT(PMU_L2_IDLE_EN) | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 806 | BIT(PMU_SCU_PD_EN) | |
| 807 | BIT(PMU_CCI_PD_EN) | |
| 808 | BIT(PMU_CLK_CORE_SRC_GATE_EN) | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 809 | BIT(PMU_ALIVE_USE_LF) | |
| 810 | BIT(PMU_SREF0_ENTER_EN) | |
| 811 | BIT(PMU_SREF1_ENTER_EN) | |
| 812 | BIT(PMU_DDRC0_GATING_EN) | |
| 813 | BIT(PMU_DDRC1_GATING_EN) | |
| 814 | BIT(PMU_DDRIO0_RET_EN) | |
| 815 | BIT(PMU_DDRIO1_RET_EN) | |
| 816 | BIT(PMU_DDRIO_RET_HW_DE_REQ) | |
Caesar Wang | 5339d18 | 2016-10-27 01:13:34 +0800 | [diff] [blame] | 817 | BIT(PMU_CENTER_PD_EN) | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 818 | BIT(PMU_PLL_PD_EN) | |
| 819 | BIT(PMU_CLK_CENTER_SRC_GATE_EN) | |
| 820 | BIT(PMU_OSC_DIS) | |
| 821 | BIT(PMU_PMU_USE_LF); |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 822 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 823 | mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN)); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 824 | mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg); |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 825 | |
Caesar Wang | fbaa360 | 2016-08-09 08:15:44 +0800 | [diff] [blame] | 826 | mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW); |
| 827 | mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K); |
| 828 | mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /* 32k iomux */ |
| 829 | } |
| 830 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 831 | static void set_hw_idle(uint32_t hw_idle) |
| 832 | { |
| 833 | mmio_setbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); |
| 834 | } |
| 835 | |
| 836 | static void clr_hw_idle(uint32_t hw_idle) |
| 837 | { |
| 838 | mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 839 | } |
| 840 | |
Caesar Wang | 5045a1c | 2016-09-10 02:47:53 +0800 | [diff] [blame] | 841 | static uint32_t iomux_status[12]; |
| 842 | static uint32_t pull_mode_status[12]; |
| 843 | static uint32_t gpio_direction[3]; |
| 844 | static uint32_t gpio_2_4_clk_gate; |
| 845 | |
| 846 | static void suspend_apio(void) |
| 847 | { |
| 848 | struct apio_info *suspend_apio; |
| 849 | int i; |
| 850 | |
| 851 | suspend_apio = plat_get_rockchip_suspend_apio(); |
| 852 | |
| 853 | if (!suspend_apio) |
| 854 | return; |
| 855 | |
| 856 | /* save gpio2 ~ gpio4 iomux and pull mode */ |
| 857 | for (i = 0; i < 12; i++) { |
| 858 | iomux_status[i] = mmio_read_32(GRF_BASE + |
| 859 | GRF_GPIO2A_IOMUX + i * 4); |
| 860 | pull_mode_status[i] = mmio_read_32(GRF_BASE + |
| 861 | GRF_GPIO2A_P + i * 4); |
| 862 | } |
| 863 | |
| 864 | /* store gpio2 ~ gpio4 clock gate state */ |
| 865 | gpio_2_4_clk_gate = (mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)) >> |
| 866 | PCLK_GPIO2_GATE_SHIFT) & 0x07; |
| 867 | |
| 868 | /* enable gpio2 ~ gpio4 clock gate */ |
| 869 | mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), |
| 870 | BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT)); |
| 871 | |
| 872 | /* save gpio2 ~ gpio4 direction */ |
| 873 | gpio_direction[0] = mmio_read_32(GPIO2_BASE + 0x04); |
| 874 | gpio_direction[1] = mmio_read_32(GPIO3_BASE + 0x04); |
| 875 | gpio_direction[2] = mmio_read_32(GPIO4_BASE + 0x04); |
| 876 | |
| 877 | /* apio1 charge gpio3a0 ~ gpio3c7 */ |
| 878 | if (suspend_apio->apio1) { |
| 879 | |
| 880 | /* set gpio3a0 ~ gpio3c7 iomux to gpio */ |
| 881 | mmio_write_32(GRF_BASE + GRF_GPIO3A_IOMUX, |
| 882 | REG_SOC_WMSK | GRF_IOMUX_GPIO); |
| 883 | mmio_write_32(GRF_BASE + GRF_GPIO3B_IOMUX, |
| 884 | REG_SOC_WMSK | GRF_IOMUX_GPIO); |
| 885 | mmio_write_32(GRF_BASE + GRF_GPIO3C_IOMUX, |
| 886 | REG_SOC_WMSK | GRF_IOMUX_GPIO); |
| 887 | |
| 888 | /* set gpio3a0 ~ gpio3c7 pull mode to pull none */ |
| 889 | mmio_write_32(GRF_BASE + GRF_GPIO3A_P, REG_SOC_WMSK | 0); |
| 890 | mmio_write_32(GRF_BASE + GRF_GPIO3B_P, REG_SOC_WMSK | 0); |
| 891 | mmio_write_32(GRF_BASE + GRF_GPIO3C_P, REG_SOC_WMSK | 0); |
| 892 | |
| 893 | /* set gpio3a0 ~ gpio3c7 to input */ |
| 894 | mmio_clrbits_32(GPIO3_BASE + 0x04, 0x00ffffff); |
| 895 | } |
| 896 | |
| 897 | /* apio2 charge gpio2a0 ~ gpio2b4 */ |
| 898 | if (suspend_apio->apio2) { |
| 899 | |
| 900 | /* set gpio2a0 ~ gpio2b4 iomux to gpio */ |
| 901 | mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX, |
| 902 | REG_SOC_WMSK | GRF_IOMUX_GPIO); |
| 903 | mmio_write_32(GRF_BASE + GRF_GPIO2B_IOMUX, |
| 904 | REG_SOC_WMSK | GRF_IOMUX_GPIO); |
| 905 | |
| 906 | /* set gpio2a0 ~ gpio2b4 pull mode to pull none */ |
| 907 | mmio_write_32(GRF_BASE + GRF_GPIO2A_P, REG_SOC_WMSK | 0); |
| 908 | mmio_write_32(GRF_BASE + GRF_GPIO2B_P, REG_SOC_WMSK | 0); |
| 909 | |
| 910 | /* set gpio2a0 ~ gpio2b4 to input */ |
| 911 | mmio_clrbits_32(GPIO2_BASE + 0x04, 0x00001fff); |
| 912 | } |
| 913 | |
| 914 | /* apio3 charge gpio2c0 ~ gpio2d4*/ |
| 915 | if (suspend_apio->apio3) { |
| 916 | |
| 917 | /* set gpio2a0 ~ gpio2b4 iomux to gpio */ |
| 918 | mmio_write_32(GRF_BASE + GRF_GPIO2C_IOMUX, |
| 919 | REG_SOC_WMSK | GRF_IOMUX_GPIO); |
| 920 | mmio_write_32(GRF_BASE + GRF_GPIO2D_IOMUX, |
| 921 | REG_SOC_WMSK | GRF_IOMUX_GPIO); |
| 922 | |
| 923 | /* set gpio2c0 ~ gpio2d4 pull mode to pull none */ |
| 924 | mmio_write_32(GRF_BASE + GRF_GPIO2C_P, REG_SOC_WMSK | 0); |
| 925 | mmio_write_32(GRF_BASE + GRF_GPIO2D_P, REG_SOC_WMSK | 0); |
| 926 | |
| 927 | /* set gpio2c0 ~ gpio2d4 to input */ |
| 928 | mmio_clrbits_32(GPIO2_BASE + 0x04, 0x1fff0000); |
| 929 | } |
| 930 | |
| 931 | /* apio4 charge gpio4c0 ~ gpio4c7, gpio4d0 ~ gpio4d6 */ |
| 932 | if (suspend_apio->apio4) { |
| 933 | |
| 934 | /* set gpio4c0 ~ gpio4d6 iomux to gpio */ |
| 935 | mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, |
| 936 | REG_SOC_WMSK | GRF_IOMUX_GPIO); |
| 937 | mmio_write_32(GRF_BASE + GRF_GPIO4D_IOMUX, |
| 938 | REG_SOC_WMSK | GRF_IOMUX_GPIO); |
| 939 | |
| 940 | /* set gpio4c0 ~ gpio4d6 pull mode to pull none */ |
| 941 | mmio_write_32(GRF_BASE + GRF_GPIO4C_P, REG_SOC_WMSK | 0); |
| 942 | mmio_write_32(GRF_BASE + GRF_GPIO4D_P, REG_SOC_WMSK | 0); |
| 943 | |
| 944 | /* set gpio4c0 ~ gpio4d6 to input */ |
| 945 | mmio_clrbits_32(GPIO4_BASE + 0x04, 0x7fff0000); |
| 946 | } |
| 947 | |
| 948 | /* apio5 charge gpio3d0 ~ gpio3d7, gpio4a0 ~ gpio4a7*/ |
| 949 | if (suspend_apio->apio5) { |
| 950 | /* set gpio3d0 ~ gpio4a7 iomux to gpio */ |
| 951 | mmio_write_32(GRF_BASE + GRF_GPIO3D_IOMUX, |
| 952 | REG_SOC_WMSK | GRF_IOMUX_GPIO); |
| 953 | mmio_write_32(GRF_BASE + GRF_GPIO4A_IOMUX, |
| 954 | REG_SOC_WMSK | GRF_IOMUX_GPIO); |
| 955 | |
| 956 | /* set gpio3d0 ~ gpio4a7 pull mode to pull none */ |
| 957 | mmio_write_32(GRF_BASE + GRF_GPIO3D_P, REG_SOC_WMSK | 0); |
| 958 | mmio_write_32(GRF_BASE + GRF_GPIO4A_P, REG_SOC_WMSK | 0); |
| 959 | |
| 960 | /* set gpio4c0 ~ gpio4d6 to input */ |
| 961 | mmio_clrbits_32(GPIO3_BASE + 0x04, 0xff000000); |
| 962 | mmio_clrbits_32(GPIO4_BASE + 0x04, 0x000000ff); |
| 963 | } |
| 964 | } |
| 965 | |
| 966 | static void resume_apio(void) |
| 967 | { |
| 968 | struct apio_info *suspend_apio; |
| 969 | int i; |
| 970 | |
| 971 | suspend_apio = plat_get_rockchip_suspend_apio(); |
| 972 | |
| 973 | if (!suspend_apio) |
| 974 | return; |
| 975 | |
| 976 | for (i = 0; i < 12; i++) { |
| 977 | mmio_write_32(GRF_BASE + GRF_GPIO2A_P + i * 4, |
| 978 | REG_SOC_WMSK | pull_mode_status[i]); |
| 979 | mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4, |
| 980 | REG_SOC_WMSK | iomux_status[i]); |
| 981 | } |
| 982 | |
| 983 | /* set gpio2 ~ gpio4 direction back to store value */ |
| 984 | mmio_write_32(GPIO2_BASE + 0x04, gpio_direction[0]); |
| 985 | mmio_write_32(GPIO3_BASE + 0x04, gpio_direction[1]); |
| 986 | mmio_write_32(GPIO4_BASE + 0x04, gpio_direction[2]); |
| 987 | |
| 988 | /* set gpio2 ~ gpio4 clock gate back to store value */ |
| 989 | mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), |
| 990 | BITS_WITH_WMASK(gpio_2_4_clk_gate, 0x07, |
| 991 | PCLK_GPIO2_GATE_SHIFT)); |
| 992 | } |
| 993 | |
Caesar Wang | ef18007 | 2016-09-10 02:43:15 +0800 | [diff] [blame] | 994 | static void suspend_gpio(void) |
| 995 | { |
| 996 | struct gpio_info *suspend_gpio; |
| 997 | uint32_t count; |
| 998 | int i; |
| 999 | |
| 1000 | suspend_gpio = plat_get_rockchip_suspend_gpio(&count); |
| 1001 | |
| 1002 | for (i = 0; i < count; i++) { |
| 1003 | gpio_set_value(suspend_gpio[i].index, suspend_gpio[i].polarity); |
| 1004 | gpio_set_direction(suspend_gpio[i].index, GPIO_DIR_OUT); |
| 1005 | udelay(1); |
| 1006 | } |
| 1007 | } |
| 1008 | |
| 1009 | static void resume_gpio(void) |
| 1010 | { |
| 1011 | struct gpio_info *suspend_gpio; |
| 1012 | uint32_t count; |
| 1013 | int i; |
| 1014 | |
| 1015 | suspend_gpio = plat_get_rockchip_suspend_gpio(&count); |
| 1016 | |
| 1017 | for (i = count - 1; i >= 0; i--) { |
| 1018 | gpio_set_value(suspend_gpio[i].index, |
| 1019 | !suspend_gpio[i].polarity); |
| 1020 | gpio_set_direction(suspend_gpio[i].index, GPIO_DIR_OUT); |
| 1021 | udelay(1); |
| 1022 | } |
| 1023 | } |
| 1024 | |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 1025 | static void m0_configure_suspend(void) |
Caesar Wang | bb22862 | 2016-10-12 01:47:51 +0800 | [diff] [blame] | 1026 | { |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 1027 | /* set PARAM to M0_FUNC_SUSPEND */ |
| 1028 | mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_SUSPEND); |
Caesar Wang | bb22862 | 2016-10-12 01:47:51 +0800 | [diff] [blame] | 1029 | } |
| 1030 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 1031 | int rockchip_soc_sys_pwr_dm_suspend(void) |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1032 | { |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1033 | uint32_t wait_cnt = 0; |
| 1034 | uint32_t status = 0; |
| 1035 | |
Derek Basehore | e13bc54 | 2017-02-24 14:31:36 +0800 | [diff] [blame] | 1036 | ddr_prepare_for_sys_suspend(); |
Caesar Wang | 5339d18 | 2016-10-27 01:13:34 +0800 | [diff] [blame] | 1037 | dmc_save(); |
| 1038 | pmu_scu_b_pwrdn(); |
| 1039 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1040 | pmu_power_domains_suspend(); |
| 1041 | set_hw_idle(BIT(PMU_CLR_CENTER1) | |
| 1042 | BIT(PMU_CLR_ALIVE) | |
| 1043 | BIT(PMU_CLR_MSCH0) | |
| 1044 | BIT(PMU_CLR_MSCH1) | |
| 1045 | BIT(PMU_CLR_CCIM0) | |
| 1046 | BIT(PMU_CLR_CCIM1) | |
| 1047 | BIT(PMU_CLR_CENTER) | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1048 | BIT(PMU_CLR_GIC)); |
| 1049 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1050 | sys_slp_config(); |
Caesar Wang | bb22862 | 2016-10-12 01:47:51 +0800 | [diff] [blame] | 1051 | |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 1052 | m0_configure_suspend(); |
| 1053 | m0_start(); |
Caesar Wang | bb22862 | 2016-10-12 01:47:51 +0800 | [diff] [blame] | 1054 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1055 | pmu_sgrf_rst_hld(); |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1056 | |
Xing Zheng | 22a9871 | 2017-02-24 14:56:41 +0800 | [diff] [blame] | 1057 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), |
Lin Huang | 30e4339 | 2017-05-04 16:02:45 +0800 | [diff] [blame] | 1058 | ((uintptr_t)&pmu_cpuson_entrypoint >> |
| 1059 | CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1060 | |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1061 | mmio_write_32(PMU_BASE + PMU_ADB400_CON, |
| 1062 | BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | |
| 1063 | BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_SW) | |
| 1064 | BIT_WITH_WMSK(PMU_PWRDWN_REQ_GIC2_CORE_B_SW)); |
| 1065 | dsb(); |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1066 | status = BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST) | |
| 1067 | BIT(PMU_PWRDWN_REQ_CORE_B_SW_ST) | |
| 1068 | BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST); |
| 1069 | while ((mmio_read_32(PMU_BASE + |
| 1070 | PMU_ADB400_ST) & status) != status) { |
| 1071 | wait_cnt++; |
| 1072 | if (wait_cnt >= MAX_WAIT_COUNT) { |
| 1073 | ERROR("%s:wait cluster-b l2(%x)\n", __func__, |
| 1074 | mmio_read_32(PMU_BASE + PMU_ADB400_ST)); |
| 1075 | panic(); |
| 1076 | } |
| 1077 | } |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1078 | mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN)); |
Caesar Wang | 5339d18 | 2016-10-27 01:13:34 +0800 | [diff] [blame] | 1079 | |
Caesar Wang | 813a89a | 2016-11-04 21:13:01 +0800 | [diff] [blame] | 1080 | secure_watchdog_disable(); |
| 1081 | |
Caesar Wang | e67b1de | 2016-08-17 17:22:10 -0700 | [diff] [blame] | 1082 | /* |
| 1083 | * Disabling PLLs/PWM/DVFS is approaching WFI which is |
| 1084 | * the last steps in suspend. |
| 1085 | */ |
Caesar Wang | ed6b9a5 | 2016-08-11 02:11:45 +0800 | [diff] [blame] | 1086 | disable_dvfs_plls(); |
| 1087 | disable_pwms(); |
| 1088 | disable_nodvfs_plls(); |
Caesar Wang | bb22862 | 2016-10-12 01:47:51 +0800 | [diff] [blame] | 1089 | |
Caesar Wang | 5045a1c | 2016-09-10 02:47:53 +0800 | [diff] [blame] | 1090 | suspend_apio(); |
Caesar Wang | ef18007 | 2016-09-10 02:43:15 +0800 | [diff] [blame] | 1091 | suspend_gpio(); |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1092 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1093 | return 0; |
| 1094 | } |
| 1095 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 1096 | int rockchip_soc_sys_pwr_dm_resume(void) |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1097 | { |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1098 | uint32_t wait_cnt = 0; |
| 1099 | uint32_t status = 0; |
| 1100 | |
Caesar Wang | 5045a1c | 2016-09-10 02:47:53 +0800 | [diff] [blame] | 1101 | resume_apio(); |
Caesar Wang | ef18007 | 2016-09-10 02:43:15 +0800 | [diff] [blame] | 1102 | resume_gpio(); |
Caesar Wang | ed6b9a5 | 2016-08-11 02:11:45 +0800 | [diff] [blame] | 1103 | enable_nodvfs_plls(); |
| 1104 | enable_pwms(); |
| 1105 | /* PWM regulators take time to come up; give 300us to be safe. */ |
| 1106 | udelay(300); |
| 1107 | enable_dvfs_plls(); |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1108 | |
Xing Zheng | 22a9871 | 2017-02-24 14:56:41 +0800 | [diff] [blame] | 1109 | secure_watchdog_enable(); |
Caesar Wang | 813a89a | 2016-11-04 21:13:01 +0800 | [diff] [blame] | 1110 | |
Caesar Wang | 5339d18 | 2016-10-27 01:13:34 +0800 | [diff] [blame] | 1111 | /* restore clk_ddrc_bpll_src_en gate */ |
| 1112 | mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), |
| 1113 | BITS_WITH_WMASK(clk_ddrc_save, 0xff, 0)); |
| 1114 | |
Caesar Wang | e67b1de | 2016-08-17 17:22:10 -0700 | [diff] [blame] | 1115 | /* |
| 1116 | * The wakeup status is not cleared by itself, we need to clear it |
| 1117 | * manually. Otherwise we will alway query some interrupt next time. |
| 1118 | * |
| 1119 | * NOTE: If the kernel needs to query this, we might want to stash it |
| 1120 | * somewhere. |
| 1121 | */ |
| 1122 | mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff); |
Caesar Wang | e67b1de | 2016-08-17 17:22:10 -0700 | [diff] [blame] | 1123 | mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00); |
| 1124 | |
Xing Zheng | 22a9871 | 2017-02-24 14:56:41 +0800 | [diff] [blame] | 1125 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1126 | (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | |
| 1127 | CPU_BOOT_ADDR_WMASK); |
| 1128 | |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1129 | mmio_write_32(PMU_BASE + PMU_CCI500_CON, |
| 1130 | WMSK_BIT(PMU_CLR_PREQ_CCI500_HW) | |
| 1131 | WMSK_BIT(PMU_CLR_QREQ_CCI500_HW) | |
| 1132 | WMSK_BIT(PMU_QGATING_CCI500_CFG)); |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1133 | dsb(); |
| 1134 | mmio_clrbits_32(PMU_BASE + PMU_PWRDN_CON, |
| 1135 | BIT(PMU_SCU_B_PWRDWN_EN)); |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1136 | |
| 1137 | mmio_write_32(PMU_BASE + PMU_ADB400_CON, |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1138 | WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | |
| 1139 | WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_SW) | |
| 1140 | WMSK_BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW) | |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1141 | WMSK_BIT(PMU_CLR_CORE_L_HW) | |
| 1142 | WMSK_BIT(PMU_CLR_CORE_L_2GIC_HW) | |
| 1143 | WMSK_BIT(PMU_CLR_GIC2_CORE_L_HW)); |
| 1144 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1145 | status = BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST) | |
| 1146 | BIT(PMU_PWRDWN_REQ_CORE_B_SW_ST) | |
| 1147 | BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST); |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1148 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1149 | while ((mmio_read_32(PMU_BASE + |
| 1150 | PMU_ADB400_ST) & status)) { |
| 1151 | wait_cnt++; |
| 1152 | if (wait_cnt >= MAX_WAIT_COUNT) { |
| 1153 | ERROR("%s:wait cluster-b l2(%x)\n", __func__, |
| 1154 | mmio_read_32(PMU_BASE + PMU_ADB400_ST)); |
| 1155 | panic(); |
| 1156 | } |
| 1157 | } |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1158 | |
Caesar Wang | c7aaa78 | 2016-08-09 07:53:41 +0800 | [diff] [blame] | 1159 | pmu_sgrf_rst_hld_release(); |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1160 | pmu_scu_b_pwrup(); |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1161 | pmu_power_domains_resume(); |
Caesar Wang | 5339d18 | 2016-10-27 01:13:34 +0800 | [diff] [blame] | 1162 | |
| 1163 | restore_dpll(); |
| 1164 | sram_func_set_ddrctl_pll(DPLL_ID); |
| 1165 | restore_abpll(); |
| 1166 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1167 | clr_hw_idle(BIT(PMU_CLR_CENTER1) | |
| 1168 | BIT(PMU_CLR_ALIVE) | |
| 1169 | BIT(PMU_CLR_MSCH0) | |
| 1170 | BIT(PMU_CLR_MSCH1) | |
| 1171 | BIT(PMU_CLR_CCIM0) | |
| 1172 | BIT(PMU_CLR_CCIM1) | |
| 1173 | BIT(PMU_CLR_CENTER) | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1174 | BIT(PMU_CLR_GIC)); |
Caesar Wang | a8216ab | 2016-09-13 11:15:00 +0800 | [diff] [blame] | 1175 | |
| 1176 | plat_rockchip_gic_cpuif_enable(); |
Xing Zheng | 93280b7 | 2016-10-26 21:25:26 +0800 | [diff] [blame] | 1177 | m0_stop(); |
Caesar Wang | bb22862 | 2016-10-12 01:47:51 +0800 | [diff] [blame] | 1178 | |
Derek Basehore | e13bc54 | 2017-02-24 14:31:36 +0800 | [diff] [blame] | 1179 | ddr_prepare_for_sys_resume(); |
| 1180 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1181 | return 0; |
| 1182 | } |
| 1183 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 1184 | void __dead2 rockchip_soc_soft_reset(void) |
Caesar Wang | a5dc64d | 2016-05-25 19:04:47 +0800 | [diff] [blame] | 1185 | { |
| 1186 | struct gpio_info *rst_gpio; |
| 1187 | |
Caesar Wang | ef18007 | 2016-09-10 02:43:15 +0800 | [diff] [blame] | 1188 | rst_gpio = plat_get_rockchip_gpio_reset(); |
Caesar Wang | a5dc64d | 2016-05-25 19:04:47 +0800 | [diff] [blame] | 1189 | |
| 1190 | if (rst_gpio) { |
| 1191 | gpio_set_direction(rst_gpio->index, GPIO_DIR_OUT); |
| 1192 | gpio_set_value(rst_gpio->index, rst_gpio->polarity); |
| 1193 | } else { |
| 1194 | soc_global_soft_reset(); |
| 1195 | } |
| 1196 | |
| 1197 | while (1) |
| 1198 | ; |
| 1199 | } |
| 1200 | |
tony.xie | 422d51c | 2017-03-01 11:05:17 +0800 | [diff] [blame] | 1201 | void __dead2 rockchip_soc_system_off(void) |
Caesar Wang | d1b9d2d | 2016-05-25 19:05:19 +0800 | [diff] [blame] | 1202 | { |
| 1203 | struct gpio_info *poweroff_gpio; |
| 1204 | |
Caesar Wang | ef18007 | 2016-09-10 02:43:15 +0800 | [diff] [blame] | 1205 | poweroff_gpio = plat_get_rockchip_gpio_poweroff(); |
Caesar Wang | d1b9d2d | 2016-05-25 19:05:19 +0800 | [diff] [blame] | 1206 | |
| 1207 | if (poweroff_gpio) { |
| 1208 | /* |
| 1209 | * if use tsadc over temp pin(GPIO1A6) as shutdown gpio, |
| 1210 | * need to set this pin iomux back to gpio function |
| 1211 | */ |
| 1212 | if (poweroff_gpio->index == TSADC_INT_PIN) { |
| 1213 | mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX, |
| 1214 | GPIO1A6_IOMUX); |
| 1215 | } |
| 1216 | gpio_set_direction(poweroff_gpio->index, GPIO_DIR_OUT); |
| 1217 | gpio_set_value(poweroff_gpio->index, poweroff_gpio->polarity); |
| 1218 | } else { |
| 1219 | WARN("Do nothing when system off\n"); |
| 1220 | } |
| 1221 | |
| 1222 | while (1) |
| 1223 | ; |
| 1224 | } |
| 1225 | |
Lin Huang | 30e4339 | 2017-05-04 16:02:45 +0800 | [diff] [blame] | 1226 | void rockchip_plat_mmu_el3(void) |
| 1227 | { |
| 1228 | size_t sram_size; |
| 1229 | |
| 1230 | /* sram.text size */ |
| 1231 | sram_size = (char *)&__bl31_sram_text_end - |
| 1232 | (char *)&__bl31_sram_text_start; |
| 1233 | mmap_add_region((unsigned long)&__bl31_sram_text_start, |
| 1234 | (unsigned long)&__bl31_sram_text_start, |
| 1235 | sram_size, MT_MEMORY | MT_RO | MT_SECURE); |
| 1236 | |
| 1237 | /* sram.data size */ |
| 1238 | sram_size = (char *)&__bl31_sram_data_end - |
| 1239 | (char *)&__bl31_sram_data_start; |
| 1240 | mmap_add_region((unsigned long)&__bl31_sram_data_start, |
| 1241 | (unsigned long)&__bl31_sram_data_start, |
| 1242 | sram_size, MT_MEMORY | MT_RW | MT_SECURE); |
| 1243 | |
| 1244 | sram_size = (char *)&__bl31_sram_stack_end - |
| 1245 | (char *)&__bl31_sram_stack_start; |
| 1246 | mmap_add_region((unsigned long)&__bl31_sram_stack_start, |
| 1247 | (unsigned long)&__bl31_sram_stack_start, |
| 1248 | sram_size, MT_MEMORY | MT_RW | MT_SECURE); |
| 1249 | |
| 1250 | sram_size = (char *)&__sram_incbin_end - (char *)&__sram_incbin_start; |
| 1251 | mmap_add_region((unsigned long)&__sram_incbin_start, |
| 1252 | (unsigned long)&__sram_incbin_start, |
| 1253 | sram_size, MT_NON_CACHEABLE | MT_RW | MT_SECURE); |
| 1254 | } |
| 1255 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1256 | void plat_rockchip_pmu_init(void) |
| 1257 | { |
| 1258 | uint32_t cpu; |
| 1259 | |
| 1260 | rockchip_pd_lock_init(); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1261 | |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1262 | /* register requires 32bits mode, switch it to 32 bits */ |
| 1263 | cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot; |
| 1264 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1265 | for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) |
| 1266 | cpuson_flags[cpu] = 0; |
| 1267 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1268 | for (cpu = 0; cpu < PLATFORM_CLUSTER_COUNT; cpu++) |
| 1269 | clst_warmboot_data[cpu] = 0; |
| 1270 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1271 | /* config cpu's warm boot address */ |
Xing Zheng | 22a9871 | 2017-02-24 14:56:41 +0800 | [diff] [blame] | 1272 | mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1273 | (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1274 | CPU_BOOT_ADDR_WMASK); |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 1275 | mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE); |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1276 | |
Caesar Wang | 3e8548b | 2016-08-25 06:31:32 +0800 | [diff] [blame] | 1277 | /* |
| 1278 | * Enable Schmitt trigger for better 32 kHz input signal, which is |
| 1279 | * important for suspend/resume reliability among other things. |
| 1280 | */ |
| 1281 | mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_SMT, GPIO0A0_SMT_ENABLE); |
| 1282 | |
Caesar Wang | 34d18d3 | 2016-08-25 06:29:46 +0800 | [diff] [blame] | 1283 | init_pmu_counts(); |
| 1284 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1285 | nonboot_cpus_off(); |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 1286 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1287 | INFO("%s(%d): pd status %x\n", __func__, __LINE__, |
| 1288 | mmio_read_32(PMU_BASE + PMU_PWRDN_ST)); |
| 1289 | } |