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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +01002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <lib/bakery_lock.h>
8#include <lib/mmio.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +00009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
Dan Handley2b6b5742015-03-19 19:17:53 +000011#include <plat_arm.h>
Soby Mathew523d6332015-01-08 18:02:19 +000012#include "../../fvp_private.h"
Dan Handley4d2e49d2014-04-11 11:52:12 +010013#include "fvp_pwrc.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010014
15/*
16 * TODO: Someday there will be a generic power controller api. At the moment
17 * each platform has its own pwrc so just exporting functions is fine.
18 */
Jeenu Viswambharan749d25b2017-08-23 14:12:59 +010019ARM_INSTANTIATE_LOCK;
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
Soby Mathewa0fedc42016-06-16 14:52:04 +010021unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010022{
Andrew Thoelke958cc022014-06-09 12:54:15 +010023 return PSYSR_WK(fvp_pwrc_read_psysr(mpidr));
Achin Gupta4f6ad662013-10-25 09:08:21 +010024}
25
Soby Mathewa0fedc42016-06-16 14:52:04 +010026unsigned int fvp_pwrc_read_psysr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010027{
Andrew Thoelke958cc022014-06-09 12:54:15 +010028 unsigned int rc;
Dan Handley2b6b5742015-03-19 19:17:53 +000029 arm_lock_get();
Achin Gupta4f6ad662013-10-25 09:08:21 +010030 mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
31 rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
Dan Handley2b6b5742015-03-19 19:17:53 +000032 arm_lock_release();
Achin Gupta4f6ad662013-10-25 09:08:21 +010033 return rc;
34}
35
Soby Mathewa0fedc42016-06-16 14:52:04 +010036void fvp_pwrc_write_pponr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010037{
Dan Handley2b6b5742015-03-19 19:17:53 +000038 arm_lock_get();
Achin Gupta4f6ad662013-10-25 09:08:21 +010039 mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
Dan Handley2b6b5742015-03-19 19:17:53 +000040 arm_lock_release();
Achin Gupta4f6ad662013-10-25 09:08:21 +010041}
42
Soby Mathewa0fedc42016-06-16 14:52:04 +010043void fvp_pwrc_write_ppoffr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010044{
Dan Handley2b6b5742015-03-19 19:17:53 +000045 arm_lock_get();
Achin Gupta4f6ad662013-10-25 09:08:21 +010046 mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
Dan Handley2b6b5742015-03-19 19:17:53 +000047 arm_lock_release();
Achin Gupta4f6ad662013-10-25 09:08:21 +010048}
49
Soby Mathewa0fedc42016-06-16 14:52:04 +010050void fvp_pwrc_set_wen(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010051{
Dan Handley2b6b5742015-03-19 19:17:53 +000052 arm_lock_get();
Achin Gupta4f6ad662013-10-25 09:08:21 +010053 mmio_write_32(PWRC_BASE + PWKUPR_OFF,
54 (unsigned int) (PWKUPR_WEN | mpidr));
Dan Handley2b6b5742015-03-19 19:17:53 +000055 arm_lock_release();
Achin Gupta4f6ad662013-10-25 09:08:21 +010056}
57
Soby Mathewa0fedc42016-06-16 14:52:04 +010058void fvp_pwrc_clr_wen(u_register_t mpidr)
Achin Guptab127cdb2013-11-12 16:40:00 +000059{
Dan Handley2b6b5742015-03-19 19:17:53 +000060 arm_lock_get();
Achin Guptab127cdb2013-11-12 16:40:00 +000061 mmio_write_32(PWRC_BASE + PWKUPR_OFF,
62 (unsigned int) mpidr);
Dan Handley2b6b5742015-03-19 19:17:53 +000063 arm_lock_release();
Achin Guptab127cdb2013-11-12 16:40:00 +000064}
65
Soby Mathewa0fedc42016-06-16 14:52:04 +010066void fvp_pwrc_write_pcoffr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +010067{
Dan Handley2b6b5742015-03-19 19:17:53 +000068 arm_lock_get();
Achin Gupta4f6ad662013-10-25 09:08:21 +010069 mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
Dan Handley2b6b5742015-03-19 19:17:53 +000070 arm_lock_release();
Achin Gupta4f6ad662013-10-25 09:08:21 +010071}
72
73/* Nothing else to do here apart from initializing the lock */
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +010074void __init plat_arm_pwrc_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +010075{
Dan Handley2b6b5742015-03-19 19:17:53 +000076 arm_lock_init();
Achin Gupta4f6ad662013-10-25 09:08:21 +010077}
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