Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 31 | #include <bakery_lock.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 32 | #include <mmio.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 33 | #include "../../fvp_def.h" |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 34 | #include "../../fvp_private.h" |
Dan Handley | 4d2e49d | 2014-04-11 11:52:12 +0100 | [diff] [blame] | 35 | #include "fvp_pwrc.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 36 | |
| 37 | /* |
| 38 | * TODO: Someday there will be a generic power controller api. At the moment |
| 39 | * each platform has its own pwrc so just exporting functions is fine. |
| 40 | */ |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 41 | #if USE_COHERENT_MEM |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 42 | static bakery_lock_t pwrc_lock __attribute__ ((section("tzfw_coherent_mem"))); |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 43 | #define LOCK_ARG &pwrc_lock |
| 44 | #else |
| 45 | #define LOCK_ARG FVP_PWRC_BAKERY_ID |
| 46 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 47 | |
| 48 | unsigned int fvp_pwrc_get_cpu_wkr(unsigned long mpidr) |
| 49 | { |
Andrew Thoelke | 958cc02 | 2014-06-09 12:54:15 +0100 | [diff] [blame] | 50 | return PSYSR_WK(fvp_pwrc_read_psysr(mpidr)); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 51 | } |
| 52 | |
| 53 | unsigned int fvp_pwrc_read_psysr(unsigned long mpidr) |
| 54 | { |
Andrew Thoelke | 958cc02 | 2014-06-09 12:54:15 +0100 | [diff] [blame] | 55 | unsigned int rc; |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 56 | fvp_lock_get(LOCK_ARG); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 57 | mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr); |
| 58 | rc = mmio_read_32(PWRC_BASE + PSYSR_OFF); |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 59 | fvp_lock_release(LOCK_ARG); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 60 | return rc; |
| 61 | } |
| 62 | |
| 63 | void fvp_pwrc_write_pponr(unsigned long mpidr) |
| 64 | { |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 65 | fvp_lock_get(LOCK_ARG); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 66 | mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr); |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 67 | fvp_lock_release(LOCK_ARG); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | void fvp_pwrc_write_ppoffr(unsigned long mpidr) |
| 71 | { |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 72 | fvp_lock_get(LOCK_ARG); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 73 | mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr); |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 74 | fvp_lock_release(LOCK_ARG); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 75 | } |
| 76 | |
Achin Gupta | b127cdb | 2013-11-12 16:40:00 +0000 | [diff] [blame] | 77 | void fvp_pwrc_set_wen(unsigned long mpidr) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 78 | { |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 79 | fvp_lock_get(LOCK_ARG); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 80 | mmio_write_32(PWRC_BASE + PWKUPR_OFF, |
| 81 | (unsigned int) (PWKUPR_WEN | mpidr)); |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 82 | fvp_lock_release(LOCK_ARG); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 83 | } |
| 84 | |
Achin Gupta | b127cdb | 2013-11-12 16:40:00 +0000 | [diff] [blame] | 85 | void fvp_pwrc_clr_wen(unsigned long mpidr) |
| 86 | { |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 87 | fvp_lock_get(LOCK_ARG); |
Achin Gupta | b127cdb | 2013-11-12 16:40:00 +0000 | [diff] [blame] | 88 | mmio_write_32(PWRC_BASE + PWKUPR_OFF, |
| 89 | (unsigned int) mpidr); |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 90 | fvp_lock_release(LOCK_ARG); |
Achin Gupta | b127cdb | 2013-11-12 16:40:00 +0000 | [diff] [blame] | 91 | } |
| 92 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 93 | void fvp_pwrc_write_pcoffr(unsigned long mpidr) |
| 94 | { |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 95 | fvp_lock_get(LOCK_ARG); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 96 | mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr); |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 97 | fvp_lock_release(LOCK_ARG); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | /* Nothing else to do here apart from initializing the lock */ |
| 101 | int fvp_pwrc_setup(void) |
| 102 | { |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame^] | 103 | fvp_lock_init(LOCK_ARG); |
| 104 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | |
| 109 | |