Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 8a47311 | 2017-06-13 17:59:17 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __PLATFORM_DEF_H__ |
| 8 | #define __PLATFORM_DEF_H__ |
| 9 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 10 | #include <arm_def.h> |
| 11 | #include <board_arm_def.h> |
| 12 | #include <board_css_def.h> |
| 13 | #include <common_def.h> |
| 14 | #include <css_def.h> |
| 15 | #include <soc_css_def.h> |
| 16 | #include <tzc400.h> |
| 17 | #include <v2m_def.h> |
Sandrine Bailleux | 1fe4336 | 2014-07-17 09:56:29 +0100 | [diff] [blame] | 18 | #include "../juno_def.h" |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 19 | |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 20 | /* Required platform porting definitions */ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 21 | /* Juno supports system power domain */ |
| 22 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
| 23 | #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 24 | JUNO_CLUSTER_COUNT + \ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 25 | PLATFORM_CORE_COUNT) |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 26 | #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ |
| 27 | JUNO_CLUSTER1_CORE_COUNT) |
| 28 | |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 29 | /* Cryptocell HW Base address */ |
| 30 | #define PLAT_CRYPTOCELL_BASE 0x60050000 |
| 31 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 32 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 33 | * Other platform porting definitions are provided by included headers |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 34 | */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 35 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 36 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 37 | * Required ARM standard platform porting definitions |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 38 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 39 | #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 40 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 41 | /* Use the bypass address */ |
| 42 | #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 43 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 44 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 45 | * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB |
| 46 | * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of |
| 47 | * flash |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 48 | */ |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 49 | #if TRUSTED_BOARD_BOOT |
| 50 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 51 | #else |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 52 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 |
| 53 | #endif /* TRUSTED_BOARD_BOOT */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 54 | |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 55 | /* |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 56 | * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 57 | * defined for ARM development platforms. |
| 58 | */ |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 59 | #if ARM_BOARD_OPTIMISE_MEM |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 60 | /* |
| 61 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 62 | * plat_arm_mmap array defined for each BL stage. |
| 63 | */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 64 | #ifdef IMAGE_BL1 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 65 | # define PLAT_ARM_MMAP_ENTRIES 7 |
| 66 | # define MAX_XLAT_TABLES 4 |
| 67 | #endif |
| 68 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 69 | #ifdef IMAGE_BL2 |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 70 | #ifdef SPD_opteed |
| 71 | # define PLAT_ARM_MMAP_ENTRIES 9 |
| 72 | # define MAX_XLAT_TABLES 4 |
| 73 | #else |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 74 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 75 | # define MAX_XLAT_TABLES 3 |
| 76 | #endif |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 77 | #endif |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 78 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 79 | #ifdef IMAGE_BL2U |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 80 | # define PLAT_ARM_MMAP_ENTRIES 4 |
| 81 | # define MAX_XLAT_TABLES 3 |
| 82 | #endif |
| 83 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 84 | #ifdef IMAGE_BL31 |
Soby Mathew | cbafd7a | 2016-11-14 12:44:32 +0000 | [diff] [blame] | 85 | # if CSS_USE_SCMI_DRIVER |
| 86 | # define PLAT_ARM_MMAP_ENTRIES 6 |
| 87 | # define MAX_XLAT_TABLES 3 |
| 88 | # else |
| 89 | # define PLAT_ARM_MMAP_ENTRIES 5 |
| 90 | # define MAX_XLAT_TABLES 2 |
| 91 | # endif |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 92 | #endif |
| 93 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 94 | #ifdef IMAGE_BL32 |
Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 95 | # define PLAT_ARM_MMAP_ENTRIES 5 |
| 96 | # define MAX_XLAT_TABLES 4 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 97 | #endif |
| 98 | |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 99 | /* |
| 100 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 101 | * plus a little space for growth. |
| 102 | */ |
| 103 | #if TRUSTED_BOARD_BOOT |
| 104 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000 |
| 105 | #else |
| 106 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 |
| 107 | #endif |
| 108 | |
| 109 | /* |
| 110 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 111 | * little space for growth. |
| 112 | */ |
| 113 | #if TRUSTED_BOARD_BOOT |
Soby Mathew | 8a47311 | 2017-06-13 17:59:17 +0100 | [diff] [blame] | 114 | # define PLAT_ARM_MAX_BL2_SIZE 0x18000 |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 115 | #else |
| 116 | # define PLAT_ARM_MAX_BL2_SIZE 0xC000 |
| 117 | #endif |
| 118 | |
| 119 | /* |
| 120 | * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a |
| 121 | * little space for growth. |
| 122 | */ |
| 123 | #define PLAT_ARM_MAX_BL31_SIZE 0x1D000 |
| 124 | |
| 125 | #endif /* ARM_BOARD_OPTIMISE_MEM */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 126 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 127 | /* CCI related constants */ |
| 128 | #define PLAT_ARM_CCI_BASE 0x2c090000 |
| 129 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 130 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 131 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 132 | /* System timer related constants */ |
| 133 | #define PLAT_ARM_NSTIMER_FRAME_ID 1 |
| 134 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 135 | /* TZC related constants */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 136 | #define PLAT_ARM_TZC_BASE 0x2a4a0000 |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 137 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 138 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ |
| 139 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ |
| 140 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ |
| 141 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ |
| 142 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ |
| 143 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ |
| 144 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ |
| 145 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ |
| 146 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ |
| 147 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 148 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 149 | /* |
| 150 | * Required ARM CSS based platform porting definitions |
| 151 | */ |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 152 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 153 | /* GIC related constants (no GICR in GIC-400) */ |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 154 | #define PLAT_ARM_GICD_BASE 0x2c010000 |
| 155 | #define PLAT_ARM_GICC_BASE 0x2c02f000 |
| 156 | #define PLAT_ARM_GICH_BASE 0x2c04f000 |
| 157 | #define PLAT_ARM_GICV_BASE 0x2c06f000 |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 158 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 159 | /* MHU related constants */ |
| 160 | #define PLAT_CSS_MHU_BASE 0x2b1f0000 |
| 161 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 162 | /* |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 163 | * Base address of the first memory region used for communication between AP |
| 164 | * and SCP. Used by the BOM and SCPI protocols. |
| 165 | * |
| 166 | * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which |
| 167 | * means the SCP/AP configuration data gets overwritten when the AP initiates |
| 168 | * communication with the SCP. The configuration data is expected to be a |
| 169 | * 32-bit word on all CSS platforms. On Juno, part of this configuration is |
| 170 | * which CPU is the primary, according to the shift and mask definitions below. |
| 171 | */ |
| 172 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) |
| 173 | #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 |
| 174 | #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 |
| 175 | |
| 176 | /* |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 177 | * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current |
| 178 | * SCP_BL2 size plus a little space for growth. |
| 179 | */ |
Soby Mathew | 8a47311 | 2017-06-13 17:59:17 +0100 | [diff] [blame] | 180 | #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x14000 |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 181 | |
| 182 | /* |
Yatharth Kochar | 8c0177f | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 183 | * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current |
| 184 | * SCP_BL2U size plus a little space for growth. |
| 185 | */ |
Soby Mathew | 8a47311 | 2017-06-13 17:59:17 +0100 | [diff] [blame] | 186 | #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000 |
Yatharth Kochar | 8c0177f | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 187 | |
| 188 | /* |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 189 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 190 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 191 | * as Group 0 interrupts. |
| 192 | */ |
| 193 | #define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ |
| 194 | ARM_G1S_IRQS, \ |
Vikram Kanigiri | f3bcea2 | 2015-06-24 17:51:09 +0100 | [diff] [blame] | 195 | JUNO_IRQ_DMA_SMMU, \ |
| 196 | JUNO_IRQ_HDLCD0_SMMU, \ |
| 197 | JUNO_IRQ_HDLCD1_SMMU, \ |
| 198 | JUNO_IRQ_USB_SMMU, \ |
| 199 | JUNO_IRQ_THIN_LINKS_SMMU, \ |
| 200 | JUNO_IRQ_SEC_I2C, \ |
| 201 | JUNO_IRQ_GPU_SMMU_1, \ |
| 202 | JUNO_IRQ_ETR_SMMU |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 203 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 204 | #define PLAT_ARM_G0_IRQS ARM_G0_IRQS |
| 205 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 206 | /* |
| 207 | * Required ARM CSS SoC based platform porting definitions |
| 208 | */ |
| 209 | |
| 210 | /* CSS SoC NIC-400 Global Programmers View (GPV) */ |
| 211 | #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 212 | |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 213 | #endif /* __PLATFORM_DEF_H__ */ |