Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 1 | /* |
Summer Qin | 13b95c2 | 2018-03-02 15:51:14 +0800 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __PLATFORM_DEF_H__ |
| 8 | #define __PLATFORM_DEF_H__ |
| 9 | |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 10 | /* Enable the dynamic translation tables library. */ |
| 11 | #ifdef AARCH32 |
| 12 | # if defined(IMAGE_BL32) && RESET_TO_SP_MIN |
| 13 | # define PLAT_XLAT_TABLES_DYNAMIC 1 |
| 14 | # endif |
| 15 | #else |
| 16 | # if defined(IMAGE_BL31) && RESET_TO_BL31 |
| 17 | # define PLAT_XLAT_TABLES_DYNAMIC 1 |
| 18 | # endif |
| 19 | #endif /* AARCH32 */ |
| 20 | |
| 21 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 22 | #include <arm_def.h> |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 23 | #include <board_css_def.h> |
| 24 | #include <common_def.h> |
| 25 | #include <css_def.h> |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 26 | #if TRUSTED_BOARD_BOOT |
| 27 | #include <mbedtls_config.h> |
| 28 | #endif |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 29 | #include <soc_css_def.h> |
| 30 | #include <tzc400.h> |
| 31 | #include <v2m_def.h> |
Sandrine Bailleux | 1fe4336 | 2014-07-17 09:56:29 +0100 | [diff] [blame] | 32 | #include "../juno_def.h" |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 33 | |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 34 | /* Required platform porting definitions */ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 35 | /* Juno supports system power domain */ |
| 36 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
| 37 | #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 38 | JUNO_CLUSTER_COUNT + \ |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 39 | PLATFORM_CORE_COUNT) |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 40 | #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ |
| 41 | JUNO_CLUSTER1_CORE_COUNT) |
| 42 | |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 43 | /* Cryptocell HW Base address */ |
| 44 | #define PLAT_CRYPTOCELL_BASE 0x60050000 |
| 45 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 46 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 47 | * Other platform porting definitions are provided by included headers |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 48 | */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 49 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 50 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 51 | * Required ARM standard platform porting definitions |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 52 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 53 | #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 54 | |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 55 | #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ |
| 56 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 57 | /* Use the bypass address */ |
| 58 | #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 59 | |
Chris Kay | 42fbdfc | 2018-05-10 14:27:45 +0100 | [diff] [blame] | 60 | #define NSRAM_BASE 0x2e000000 |
| 61 | #define NSRAM_SIZE 0x00008000 /* 32KB */ |
| 62 | |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 63 | /* virtual address used by dynamic mem_protect for chunk_base */ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 64 | #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 65 | |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 66 | /* |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 67 | * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB |
| 68 | * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of |
| 69 | * flash |
Juan Castillo | 6ba59eb | 2014-11-07 09:44:58 +0000 | [diff] [blame] | 70 | */ |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 71 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 |
| 72 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 73 | #if TRUSTED_BOARD_BOOT |
| 74 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 75 | #else |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 76 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 |
| 77 | #endif /* TRUSTED_BOARD_BOOT */ |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 78 | |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 79 | /* |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 80 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 81 | * plat_arm_mmap array defined for each BL stage. |
| 82 | */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 83 | #ifdef IMAGE_BL1 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 84 | # define PLAT_ARM_MMAP_ENTRIES 7 |
| 85 | # define MAX_XLAT_TABLES 4 |
| 86 | #endif |
| 87 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 88 | #ifdef IMAGE_BL2 |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 89 | #ifdef SPD_opteed |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 90 | # define PLAT_ARM_MMAP_ENTRIES 11 |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 91 | # define MAX_XLAT_TABLES 5 |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 92 | #else |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 93 | # define PLAT_ARM_MMAP_ENTRIES 10 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 94 | # define MAX_XLAT_TABLES 4 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 95 | #endif |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 96 | #endif |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 97 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 98 | #ifdef IMAGE_BL2U |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 99 | # define PLAT_ARM_MMAP_ENTRIES 5 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 100 | # define MAX_XLAT_TABLES 3 |
| 101 | #endif |
| 102 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 103 | #ifdef IMAGE_BL31 |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 104 | # define PLAT_ARM_MMAP_ENTRIES 7 |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 105 | # define MAX_XLAT_TABLES 3 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 106 | #endif |
| 107 | |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 108 | #ifdef IMAGE_BL32 |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 109 | # define PLAT_ARM_MMAP_ENTRIES 6 |
Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 110 | # define MAX_XLAT_TABLES 4 |
Vikram Kanigiri | eade34c | 2016-01-20 15:57:35 +0000 | [diff] [blame] | 111 | #endif |
| 112 | |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 113 | /* |
| 114 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 115 | * plus a little space for growth. |
| 116 | */ |
| 117 | #if TRUSTED_BOARD_BOOT |
Soby Mathew | b5d7830 | 2018-06-07 15:23:39 +0100 | [diff] [blame] | 118 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 119 | #else |
| 120 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 |
| 121 | #endif |
| 122 | |
| 123 | /* |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 124 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 125 | */ |
| 126 | #if USE_ROMLIB |
| 127 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 |
| 128 | #else |
| 129 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 |
| 130 | #endif |
| 131 | |
| 132 | /* |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 133 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 134 | * little space for growth. |
| 135 | */ |
| 136 | #if TRUSTED_BOARD_BOOT |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 137 | #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA |
Soby Mathew | b5d7830 | 2018-06-07 15:23:39 +0100 | [diff] [blame] | 138 | # define PLAT_ARM_MAX_BL2_SIZE 0x1F000 |
Amit Daniel Kachhap | 4a8c7f9 | 2018-03-23 11:56:23 +0530 | [diff] [blame] | 139 | #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA |
| 140 | # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 141 | #else |
Amit Daniel Kachhap | 4a8c7f9 | 2018-03-23 11:56:23 +0530 | [diff] [blame] | 142 | # define PLAT_ARM_MAX_BL2_SIZE 0x1C000 |
Qixiang Xu | de431b1 | 2017-10-13 09:23:42 +0800 | [diff] [blame] | 143 | #endif |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 144 | #else |
Antonio Nino Diaz | 64344ef | 2018-10-23 18:31:08 +0100 | [diff] [blame] | 145 | # define PLAT_ARM_MAX_BL2_SIZE 0xF000 |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 146 | #endif |
| 147 | |
| 148 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 149 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 150 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 151 | * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. |
| 152 | * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 153 | */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 154 | #define PLAT_ARM_MAX_BL31_SIZE 0x3E000 |
Antonio Nino Diaz | 30ce3ad | 2016-07-25 12:04:31 +0100 | [diff] [blame] | 155 | |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 156 | #if JUNO_AARCH32_EL3_RUNTIME |
| 157 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 158 | * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is |
| 159 | * calculated using the current BL32 PROGBITS debug size plus the sizes of |
| 160 | * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. |
| 161 | * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 162 | */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 163 | #define PLAT_ARM_MAX_BL32_SIZE 0x3E000 |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 164 | #endif |
| 165 | |
Soby Mathew | 39f9c16 | 2017-08-22 14:06:19 +0100 | [diff] [blame] | 166 | /* |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 167 | * Size of cacheable stacks |
| 168 | */ |
| 169 | #if defined(IMAGE_BL1) |
| 170 | # if TRUSTED_BOARD_BOOT |
| 171 | # define PLATFORM_STACK_SIZE 0x1000 |
| 172 | # else |
| 173 | # define PLATFORM_STACK_SIZE 0x440 |
| 174 | # endif |
| 175 | #elif defined(IMAGE_BL2) |
| 176 | # if TRUSTED_BOARD_BOOT |
| 177 | # define PLATFORM_STACK_SIZE 0x1000 |
| 178 | # else |
| 179 | # define PLATFORM_STACK_SIZE 0x400 |
| 180 | # endif |
| 181 | #elif defined(IMAGE_BL2U) |
| 182 | # define PLATFORM_STACK_SIZE 0x400 |
| 183 | #elif defined(IMAGE_BL31) |
| 184 | # if PLAT_XLAT_TABLES_DYNAMIC |
| 185 | # define PLATFORM_STACK_SIZE 0x800 |
| 186 | # else |
| 187 | # define PLATFORM_STACK_SIZE 0x400 |
| 188 | # endif |
| 189 | #elif defined(IMAGE_BL32) |
| 190 | # define PLATFORM_STACK_SIZE 0x440 |
| 191 | #endif |
| 192 | |
| 193 | /* |
Soby Mathew | 39f9c16 | 2017-08-22 14:06:19 +0100 | [diff] [blame] | 194 | * Since free SRAM space is scant, enable the ASSERTION message size |
| 195 | * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). |
| 196 | */ |
| 197 | #define PLAT_LOG_LEVEL_ASSERT 40 |
| 198 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 199 | /* CCI related constants */ |
| 200 | #define PLAT_ARM_CCI_BASE 0x2c090000 |
| 201 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 202 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 203 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 204 | /* System timer related constants */ |
| 205 | #define PLAT_ARM_NSTIMER_FRAME_ID 1 |
| 206 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 207 | /* TZC related constants */ |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 208 | #define PLAT_ARM_TZC_BASE 0x2a4a0000 |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 209 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 210 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ |
| 211 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ |
| 212 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ |
| 213 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ |
| 214 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ |
| 215 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ |
| 216 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ |
| 217 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ |
| 218 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ |
| 219 | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 220 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 221 | /* |
| 222 | * Required ARM CSS based platform porting definitions |
| 223 | */ |
Juan Castillo | 921b877 | 2014-09-05 17:29:38 +0100 | [diff] [blame] | 224 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 225 | /* GIC related constants (no GICR in GIC-400) */ |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 226 | #define PLAT_ARM_GICD_BASE 0x2c010000 |
| 227 | #define PLAT_ARM_GICC_BASE 0x2c02f000 |
| 228 | #define PLAT_ARM_GICH_BASE 0x2c04f000 |
| 229 | #define PLAT_ARM_GICV_BASE 0x2c06f000 |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 230 | |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 231 | /* MHU related constants */ |
| 232 | #define PLAT_CSS_MHU_BASE 0x2b1f0000 |
| 233 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 234 | /* |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 235 | * Base address of the first memory region used for communication between AP |
| 236 | * and SCP. Used by the BOM and SCPI protocols. |
Soby Mathew | 1ced6b8 | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 237 | */ |
| 238 | #if !CSS_USE_SCMI_SDS_DRIVER |
| 239 | /* |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 240 | * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which |
| 241 | * means the SCP/AP configuration data gets overwritten when the AP initiates |
| 242 | * communication with the SCP. The configuration data is expected to be a |
| 243 | * 32-bit word on all CSS platforms. On Juno, part of this configuration is |
| 244 | * which CPU is the primary, according to the shift and mask definitions below. |
| 245 | */ |
| 246 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) |
| 247 | #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 |
| 248 | #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 |
Soby Mathew | 1ced6b8 | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 249 | #endif |
Vikram Kanigiri | 7208419 | 2016-02-08 16:29:30 +0000 | [diff] [blame] | 250 | |
| 251 | /* |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 252 | * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current |
| 253 | * SCP_BL2 size plus a little space for growth. |
| 254 | */ |
Soby Mathew | 8a47311 | 2017-06-13 17:59:17 +0100 | [diff] [blame] | 255 | #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x14000 |
Yatharth Kochar | f9a0f16 | 2016-09-13 17:07:57 +0100 | [diff] [blame] | 256 | |
| 257 | /* |
Yatharth Kochar | 8c0177f | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 258 | * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current |
| 259 | * SCP_BL2U size plus a little space for growth. |
| 260 | */ |
Soby Mathew | 8a47311 | 2017-06-13 17:59:17 +0100 | [diff] [blame] | 261 | #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000 |
Yatharth Kochar | 8c0177f | 2016-11-11 13:57:50 +0000 | [diff] [blame] | 262 | |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 263 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 264 | CSS_G1S_IRQ_PROPS(grp), \ |
| 265 | ARM_G1S_IRQ_PROPS(grp), \ |
| 266 | INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 267 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 268 | INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 269 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 270 | INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 271 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 272 | INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 273 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 274 | INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 275 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 276 | INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 277 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 278 | INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 279 | (grp), GIC_INTR_CFG_LEVEL), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 280 | INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 281 | (grp), GIC_INTR_CFG_LEVEL) |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 282 | |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 283 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 284 | |
Dan Handley | 7bef800 | 2015-03-19 19:22:44 +0000 | [diff] [blame] | 285 | /* |
| 286 | * Required ARM CSS SoC based platform porting definitions |
| 287 | */ |
| 288 | |
| 289 | /* CSS SoC NIC-400 Global Programmers View (GPV) */ |
| 290 | #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 291 | |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 292 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS |
| 293 | #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS |
| 294 | |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 295 | #endif /* __PLATFORM_DEF_H__ */ |