Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 9 | #include <assert.h> |
| 10 | #include <common_def.h> |
| 11 | #include <context.h> |
| 12 | #include <context_mgmt.h> |
| 13 | #include <debug.h> |
| 14 | #include <platform_def.h> |
| 15 | #include <platform.h> |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 16 | #include <string.h> |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 17 | #include <xlat_tables_v2.h> |
| 18 | |
| 19 | #include "spm_private.h" |
| 20 | #include "spm_shim_private.h" |
| 21 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 22 | /* Setup context of the Secure Partition */ |
Antonio Nino Diaz | 2875931 | 2018-05-22 16:26:48 +0100 | [diff] [blame] | 23 | void spm_sp_setup(sp_context_t *sp_ctx) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 24 | { |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 25 | cpu_context_t *ctx = &(sp_ctx->cpu_ctx); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 26 | |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 27 | /* |
| 28 | * Initialize CPU context |
| 29 | * ---------------------- |
| 30 | */ |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 31 | |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 32 | entry_point_info_t ep_info = {0}; |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 33 | |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 34 | SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE); |
Antonio Nino Diaz | 268eb5d | 2018-06-11 11:01:54 +0100 | [diff] [blame] | 35 | |
| 36 | /* Setup entrypoint and SPSR */ |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 37 | ep_info.pc = BL32_BASE; |
| 38 | ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 39 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 40 | /* |
Antonio Nino Diaz | fe7b2be | 2018-10-30 11:54:20 +0000 | [diff] [blame] | 41 | * X0: Unused (MBZ). |
| 42 | * X1: Unused (MBZ). |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 43 | * X2: cookie value (Implementation Defined) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 44 | * X3: cookie value (Implementation Defined) |
Antonio Nino Diaz | 268eb5d | 2018-06-11 11:01:54 +0100 | [diff] [blame] | 45 | * X4 to X7 = 0 |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 46 | */ |
Antonio Nino Diaz | fe7b2be | 2018-10-30 11:54:20 +0000 | [diff] [blame] | 47 | ep_info.args.arg0 = 0; |
| 48 | ep_info.args.arg1 = 0; |
Antonio Nino Diaz | 268eb5d | 2018-06-11 11:01:54 +0100 | [diff] [blame] | 49 | ep_info.args.arg2 = PLAT_SPM_COOKIE_0; |
| 50 | ep_info.args.arg3 = PLAT_SPM_COOKIE_1; |
| 51 | |
| 52 | cm_setup_context(ctx, &ep_info); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 53 | |
| 54 | /* |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 55 | * Setup translation tables |
| 56 | * ------------------------ |
| 57 | */ |
| 58 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 59 | /* This region contains the exception vectors used at S-EL1. */ |
| 60 | const mmap_region_t sel1_exception_vectors = |
| 61 | MAP_REGION_FLAT(SPM_SHIM_EXCEPTIONS_START, |
| 62 | SPM_SHIM_EXCEPTIONS_SIZE, |
| 63 | MT_CODE | MT_SECURE | MT_PRIVILEGED); |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 64 | mmap_add_region_ctx(sp_ctx->xlat_ctx_handle, |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 65 | &sel1_exception_vectors); |
| 66 | |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 67 | mmap_add_ctx(sp_ctx->xlat_ctx_handle, |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 68 | plat_get_secure_partition_mmap(NULL)); |
| 69 | |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 70 | init_xlat_tables_ctx(sp_ctx->xlat_ctx_handle); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 71 | |
| 72 | /* |
| 73 | * MMU-related registers |
| 74 | * --------------------- |
| 75 | */ |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 76 | xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle; |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 77 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 78 | uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 79 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 80 | setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table, |
| 81 | xlat_ctx->pa_max_address, xlat_ctx->va_max_address, |
| 82 | EL1_EL0_REGIME); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 83 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 84 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, |
| 85 | mmu_cfg_params[MMU_CFG_MAIR]); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 86 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 87 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, |
| 88 | mmu_cfg_params[MMU_CFG_TCR]); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 89 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 90 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1, |
| 91 | mmu_cfg_params[MMU_CFG_TTBR0]); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 92 | |
| 93 | /* Setup SCTLR_EL1 */ |
| 94 | u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); |
| 95 | |
| 96 | sctlr_el1 |= |
| 97 | /*SCTLR_EL1_RES1 |*/ |
| 98 | /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */ |
| 99 | SCTLR_UCI_BIT | |
| 100 | /* RW regions at xlat regime EL1&0 are forced to be XN. */ |
| 101 | SCTLR_WXN_BIT | |
| 102 | /* Don't trap to EL1 execution of WFI or WFE at EL0. */ |
| 103 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT | |
| 104 | /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */ |
| 105 | SCTLR_UCT_BIT | |
| 106 | /* Don't trap to EL1 execution of DZ ZVA at EL0. */ |
| 107 | SCTLR_DZE_BIT | |
| 108 | /* Enable SP Alignment check for EL0 */ |
| 109 | SCTLR_SA0_BIT | |
| 110 | /* Allow cacheable data and instr. accesses to normal memory. */ |
| 111 | SCTLR_C_BIT | SCTLR_I_BIT | |
| 112 | /* Alignment fault checking enabled when at EL1 and EL0. */ |
| 113 | SCTLR_A_BIT | |
| 114 | /* Enable MMU. */ |
| 115 | SCTLR_M_BIT |
| 116 | ; |
| 117 | |
| 118 | sctlr_el1 &= ~( |
| 119 | /* Explicit data accesses at EL0 are little-endian. */ |
| 120 | SCTLR_E0E_BIT | |
| 121 | /* Accesses to DAIF from EL0 are trapped to EL1. */ |
| 122 | SCTLR_UMA_BIT |
| 123 | ); |
| 124 | |
| 125 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); |
| 126 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 127 | /* |
| 128 | * Setup other system registers |
| 129 | * ---------------------------- |
| 130 | */ |
| 131 | |
| 132 | /* Shim Exception Vector Base Address */ |
| 133 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1, |
| 134 | SPM_SHIM_EXCEPTIONS_PTR); |
| 135 | |
| 136 | /* |
Sandrine Bailleux | 811934e | 2018-05-09 14:45:34 +0200 | [diff] [blame] | 137 | * FPEN: Allow the Secure Partition to access FP/SIMD registers. |
| 138 | * Note that SPM will not do any saving/restoring of these registers on |
| 139 | * behalf of the SP. This falls under the SP's responsibility. |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 140 | * TTA: Enable access to trace registers. |
| 141 | * ZEN (v8.2): Trap SVE instructions and access to SVE registers. |
| 142 | */ |
| 143 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1, |
Sandrine Bailleux | 811934e | 2018-05-09 14:45:34 +0200 | [diff] [blame] | 144 | CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE)); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 145 | } |