Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <lib/utils_def.h> |
| 8 | |
| 9 | #ifndef FPGA_DEF_H |
| 10 | #define FPGA_DEF_H |
| 11 | |
| 12 | /* |
Oliver Swede | 3769b3f | 2019-12-16 14:08:27 +0000 | [diff] [blame] | 13 | * These are set to large values to account for images describing systems with |
| 14 | * larger cluster configurations. |
| 15 | * |
| 16 | * For cases where the number of clusters, cores or threads is smaller than a |
| 17 | * maximum value below, this does not affect the PSCI functionality as any PEs |
| 18 | * that are present will still be indexed appropriately regardless of any empty |
| 19 | * entries in the array used to represent the topology. |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 20 | */ |
Javier Almansa Sobrino | fc78c3c | 2020-05-13 14:09:58 +0100 | [diff] [blame] | 21 | |
Andre Przywara | b1402c8 | 2020-06-25 13:10:38 +0100 | [diff] [blame] | 22 | #define FPGA_MAX_CLUSTER_COUNT 4 |
Oliver Swede | 3769b3f | 2019-12-16 14:08:27 +0000 | [diff] [blame] | 23 | #define FPGA_MAX_CPUS_PER_CLUSTER 8 |
Andre Przywara | 7e90b10 | 2024-02-02 17:09:46 +0000 | [diff] [blame^] | 24 | #define FPGA_MAX_PE_PER_CPU 2 |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 25 | |
| 26 | #define FPGA_PRIMARY_CPU 0x0 |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 27 | /******************************************************************************* |
| 28 | * FPGA image memory map related constants |
| 29 | ******************************************************************************/ |
| 30 | |
Andre Przywara | db96806 | 2020-04-09 10:25:43 +0100 | [diff] [blame] | 31 | /* |
| 32 | * UART base address, just for the crash console, as a fallback. |
| 33 | * The actual console UART address is taken from the DT. |
| 34 | */ |
| 35 | #define PLAT_FPGA_CRASH_UART_BASE 0x7ff80000 |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 36 | |
Andre Przywara | eec45eb | 2020-01-24 15:02:27 +0000 | [diff] [blame] | 37 | #define FPGA_DEFAULT_TIMER_FREQUENCY 10000000 |
Oliver Swede | 20e0137 | 2019-12-02 13:33:40 +0000 | [diff] [blame] | 38 | |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 39 | #endif |