| Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <lib/utils_def.h> |
| 8 | |
| 9 | #ifndef FPGA_DEF_H |
| 10 | #define FPGA_DEF_H |
| 11 | |
| 12 | /* |
| 13 | * The initial FPGA image configures a system with 2 clusters, 1 core in each, |
| 14 | * and multi-threading is unimplemented. |
| 15 | */ |
| 16 | #define FPGA_MAX_CLUSTER_COUNT 2 |
| 17 | #define FPGA_MAX_CPUS_PER_CLUSTER 1 |
| 18 | #define FPGA_MAX_PE_PER_CPU 1 |
| 19 | |
| 20 | #define FPGA_PRIMARY_CPU 0x0 |
| 21 | |
| 22 | /******************************************************************************* |
| 23 | * FPGA image memory map related constants |
| 24 | ******************************************************************************/ |
| 25 | |
| 26 | /* UART base address and clock frequency, as configured by the image */ |
| 27 | #define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000 |
| 28 | #define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 10000000 |
| 29 | |
| 30 | #define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE |
| 31 | #define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ |
| 32 | |
| 33 | #endif |