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Oliver Swede8fed2fe2019-11-11 11:11:06 +00001/*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <lib/utils_def.h>
8
9#ifndef FPGA_DEF_H
10#define FPGA_DEF_H
11
12/*
Oliver Swede3769b3f2019-12-16 14:08:27 +000013 * These are set to large values to account for images describing systems with
14 * larger cluster configurations.
15 *
16 * For cases where the number of clusters, cores or threads is smaller than a
17 * maximum value below, this does not affect the PSCI functionality as any PEs
18 * that are present will still be indexed appropriately regardless of any empty
19 * entries in the array used to represent the topology.
Oliver Swede8fed2fe2019-11-11 11:11:06 +000020 */
21#define FPGA_MAX_CLUSTER_COUNT 2
Oliver Swede3769b3f2019-12-16 14:08:27 +000022#define FPGA_MAX_CPUS_PER_CLUSTER 8
23#define FPGA_MAX_PE_PER_CPU 4
Oliver Swede8fed2fe2019-11-11 11:11:06 +000024
25#define FPGA_PRIMARY_CPU 0x0
Oliver Swede8fed2fe2019-11-11 11:11:06 +000026/*******************************************************************************
27 * FPGA image memory map related constants
28 ******************************************************************************/
29
Andre Przywara8b505252020-04-09 10:10:09 +010030/* UART base address, as configured by the image */
Oliver Swede8fed2fe2019-11-11 11:11:06 +000031#define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000
Oliver Swede8fed2fe2019-11-11 11:11:06 +000032#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE
Oliver Swede8fed2fe2019-11-11 11:11:06 +000033
Andre Przywaraeec45eb2020-01-24 15:02:27 +000034#define FPGA_DEFAULT_TIMER_FREQUENCY 10000000
Oliver Swede20e01372019-12-02 13:33:40 +000035
Oliver Swede8fed2fe2019-11-11 11:11:06 +000036#endif