plat/arm/board/arm_fpga: Initialize the System Counter
This sets the frequency of the system counter so that the Delay Timer
driver programs the correct value to CNTCRL. This value depends on
the FPGA image being used, and is 10MHz for the initial test image.
Once configured, the BL31 platform setup sequence then enables the
system counter.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a
diff --git a/plat/arm/board/arm_fpga/fpga_def.h b/plat/arm/board/arm_fpga/fpga_def.h
index 8c542e0..0f817fe 100644
--- a/plat/arm/board/arm_fpga/fpga_def.h
+++ b/plat/arm/board/arm_fpga/fpga_def.h
@@ -30,4 +30,7 @@
#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE
#define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ
+#define FPGA_TIMER_FREQUENCY 10000000
+#define FPGA_TIMER_BASE 0x2a830000
+
#endif