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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Sami Mujawar5eb649d2019-05-10 08:52:07 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00006
7#include <assert.h>
8
9#include <platform_def.h>
10
Dan Handley9df48042015-03-19 18:58:55 +000011#include <arch.h>
12#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <common/debug.h>
14#include <common/romlib.h>
15#include <lib/mmio.h>
16#include <lib/xlat_tables/xlat_tables_compat.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000017#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018#include <plat/common/platform.h>
19#include <services/secure_partition.h>
20
Dan Handley9df48042015-03-19 18:58:55 +000021/* Weak definitions may be overridden in specific ARM standard platform */
22#pragma weak plat_get_ns_image_entrypoint
Vikram Kanigiri07035432015-11-12 18:52:34 +000023#pragma weak plat_arm_get_mmap
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010024
25/* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
26 * conflicts with the definition in plat/common. */
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010027#pragma weak plat_get_syscnt_freq2
Roberto Vargase3adc372018-05-23 09:27:06 +010028
29
30void arm_setup_romlib(void)
31{
32#if USE_ROMLIB
33 if (!rom_lib_init(ROMLIB_VERSION))
34 panic();
35#endif
36}
Dan Handley9df48042015-03-19 18:58:55 +000037
Soby Mathew21f93612016-03-23 10:11:10 +000038uintptr_t plat_get_ns_image_entrypoint(void)
Dan Handley9df48042015-03-19 18:58:55 +000039{
Soby Mathew4876ae32016-05-09 17:20:10 +010040#ifdef PRELOADED_BL33_BASE
41 return PRELOADED_BL33_BASE;
42#else
Sandrine Bailleuxafa91db2019-01-31 15:01:32 +010043 return PLAT_ARM_NS_IMAGE_BASE;
Soby Mathew4876ae32016-05-09 17:20:10 +010044#endif
Dan Handley9df48042015-03-19 18:58:55 +000045}
46
47/*******************************************************************************
48 * Gets SPSR for BL32 entry
49 ******************************************************************************/
50uint32_t arm_get_spsr_for_bl32_entry(void)
51{
52 /*
53 * The Secure Payload Dispatcher service is responsible for
Juan Castillo7d199412015-12-14 09:35:25 +000054 * setting the SPSR prior to entry into the BL32 image.
Dan Handley9df48042015-03-19 18:58:55 +000055 */
56 return 0;
57}
58
59/*******************************************************************************
60 * Gets SPSR for BL33 entry
61 ******************************************************************************/
Julius Werner8e0ef0f2019-07-09 14:02:43 -070062#ifdef __aarch64__
Dan Handley9df48042015-03-19 18:58:55 +000063uint32_t arm_get_spsr_for_bl33_entry(void)
64{
Dan Handley9df48042015-03-19 18:58:55 +000065 unsigned int mode;
66 uint32_t spsr;
67
68 /* Figure out what mode we enter the non-secure world in */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000069 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
Dan Handley9df48042015-03-19 18:58:55 +000070
71 /*
72 * TODO: Consider the possibility of specifying the SPSR in
73 * the FIP ToC and allowing the platform to have a say as
74 * well.
75 */
76 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
77 return spsr;
78}
Soby Mathew0d268dc2016-07-11 14:13:56 +010079#else
80/*******************************************************************************
81 * Gets SPSR for BL33 entry
82 ******************************************************************************/
83uint32_t arm_get_spsr_for_bl33_entry(void)
84{
85 unsigned int hyp_status, mode, spsr;
86
87 hyp_status = GET_VIRT_EXT(read_id_pfr1());
88
89 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
90
91 /*
92 * TODO: Consider the possibility of specifying the SPSR in
93 * the FIP ToC and allowing the platform to have a say as
94 * well.
95 */
96 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
97 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
98 return spsr;
99}
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700100#endif /* __aarch64__ */
Dan Handley9df48042015-03-19 18:58:55 +0000101
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100102/*******************************************************************************
103 * Configures access to the system counter timer module.
104 ******************************************************************************/
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800105#ifdef ARM_SYS_TIMCTL_BASE
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100106void arm_configure_sys_timer(void)
107{
108 unsigned int reg_val;
109
Soby Mathew2d9f7952018-06-11 16:21:30 +0100110 /* Read the frequency of the system counter */
111 unsigned int freq_val = plat_get_syscnt_freq2();
112
Juan Castilloaadf19a2015-11-06 16:02:32 +0000113#if ARM_CONFIG_CNTACR
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000114 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT);
115 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT);
116 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100117 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
Juan Castilloaadf19a2015-11-06 16:02:32 +0000118#endif /* ARM_CONFIG_CNTACR */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100119
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000120 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100121 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
Soby Mathew2d9f7952018-06-11 16:21:30 +0100122
123 /*
124 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ
125 * system register initialized during psci_arch_setup() is different
126 * from this and has to be updated independently.
127 */
128 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
129
Sami Mujawar5eb649d2019-05-10 08:52:07 +0100130#if defined(PLAT_juno) || defined(PLAT_n1sdp)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100131 /*
132 * Initialize CNTFRQ register in Non-secure CNTBase frame.
Sami Mujawar5eb649d2019-05-10 08:52:07 +0100133 * This is only required for Juno and N1SDP, because they do not
134 * follow ARM ARM in that the value updated in CNTFRQ is not
135 * reflected in CNTBASEN_CNTFRQ. Hence update the value manually.
Soby Mathew2d9f7952018-06-11 16:21:30 +0100136 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000137 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val);
Soby Mathew2d9f7952018-06-11 16:21:30 +0100138#endif
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100139}
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800140#endif /* ARM_SYS_TIMCTL_BASE */
Vikram Kanigiri07035432015-11-12 18:52:34 +0000141
142/*******************************************************************************
143 * Returns ARM platform specific memory map regions.
144 ******************************************************************************/
145const mmap_region_t *plat_arm_get_mmap(void)
146{
147 return plat_arm_mmap;
148}
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100149
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100150#ifdef ARM_SYS_CNTCTL_BASE
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100151
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100152unsigned int plat_get_syscnt_freq2(void)
153{
Sandrine Bailleuxa8ef6652016-06-03 15:00:46 +0100154 unsigned int counter_base_frequency;
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100155
156 /* Read the frequency from Frequency modes table */
157 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
158
159 /* The first entry of the frequency modes table must not be 0 */
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000160 if (counter_base_frequency == 0U)
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100161 panic();
162
163 return counter_base_frequency;
164}
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100165
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100166#endif /* ARM_SYS_CNTCTL_BASE */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100167
168#if SDEI_SUPPORT
169/*
170 * Translate SDEI entry point to PA, and perform standard ARM entry point
171 * validation on it.
172 */
173int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode)
174{
175 uint64_t par, pa;
176 uint32_t scr_el3;
177
178 /* Doing Non-secure address translation requires SCR_EL3.NS set */
179 scr_el3 = read_scr_el3();
180 write_scr_el3(scr_el3 | SCR_NS_BIT);
181 isb();
182
183 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1));
184 if (client_mode == MODE_EL2) {
185 /*
186 * Translate entry point to Physical Address using the EL2
187 * translation regime.
188 */
189 ats1e2r(ep);
190 } else {
191 /*
192 * Translate entry point to Physical Address using the EL1&0
193 * translation regime, including stage 2.
194 */
195 ats12e1r(ep);
196 }
197 isb();
198 par = read_par_el1();
199
200 /* Restore original SCRL_EL3 */
201 write_scr_el3(scr_el3);
202 isb();
203
204 /* If the translation resulted in fault, return failure */
205 if ((par & PAR_F_MASK) != 0)
206 return -1;
207
208 /* Extract Physical Address from PAR */
209 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT));
210
211 /* Perform NS entry point validation on the physical address */
212 return arm_validate_ns_entrypoint(pa);
213}
214#endif