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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Roberto Vargas2ca18d92018-02-12 12:36:17 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#include <arch.h>
7#include <arch_helpers.h>
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +01008#include <assert.h>
Yatharth Kochar3c0087a2016-04-14 14:49:37 +01009#include <debug.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <mmio.h>
11#include <plat_arm.h>
Roberto Vargas2ca18d92018-02-12 12:36:17 +000012#include <platform.h>
Roberto Vargase3adc372018-05-23 09:27:06 +010013#include <platform_def.h>
14#include <romlib.h>
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000015#include <secure_partition.h>
Antonio Nino Diaz61aff002018-10-19 16:52:22 +010016#include <xlat_tables_compat.h>
Dan Handley9df48042015-03-19 18:58:55 +000017
Dan Handley9df48042015-03-19 18:58:55 +000018/* Weak definitions may be overridden in specific ARM standard platform */
19#pragma weak plat_get_ns_image_entrypoint
Vikram Kanigiri07035432015-11-12 18:52:34 +000020#pragma weak plat_arm_get_mmap
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010021
22/* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
23 * conflicts with the definition in plat/common. */
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010024#pragma weak plat_get_syscnt_freq2
Roberto Vargase3adc372018-05-23 09:27:06 +010025
26
27void arm_setup_romlib(void)
28{
29#if USE_ROMLIB
30 if (!rom_lib_init(ROMLIB_VERSION))
31 panic();
32#endif
33}
Dan Handley9df48042015-03-19 18:58:55 +000034
Soby Mathew21f93612016-03-23 10:11:10 +000035uintptr_t plat_get_ns_image_entrypoint(void)
Dan Handley9df48042015-03-19 18:58:55 +000036{
Soby Mathew4876ae32016-05-09 17:20:10 +010037#ifdef PRELOADED_BL33_BASE
38 return PRELOADED_BL33_BASE;
39#else
Dan Handley9df48042015-03-19 18:58:55 +000040 return PLAT_ARM_NS_IMAGE_OFFSET;
Soby Mathew4876ae32016-05-09 17:20:10 +010041#endif
Dan Handley9df48042015-03-19 18:58:55 +000042}
43
44/*******************************************************************************
45 * Gets SPSR for BL32 entry
46 ******************************************************************************/
47uint32_t arm_get_spsr_for_bl32_entry(void)
48{
49 /*
50 * The Secure Payload Dispatcher service is responsible for
Juan Castillo7d199412015-12-14 09:35:25 +000051 * setting the SPSR prior to entry into the BL32 image.
Dan Handley9df48042015-03-19 18:58:55 +000052 */
53 return 0;
54}
55
56/*******************************************************************************
57 * Gets SPSR for BL33 entry
58 ******************************************************************************/
Soby Mathew0d268dc2016-07-11 14:13:56 +010059#ifndef AARCH32
Dan Handley9df48042015-03-19 18:58:55 +000060uint32_t arm_get_spsr_for_bl33_entry(void)
61{
Dan Handley9df48042015-03-19 18:58:55 +000062 unsigned int mode;
63 uint32_t spsr;
64
65 /* Figure out what mode we enter the non-secure world in */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000066 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
Dan Handley9df48042015-03-19 18:58:55 +000067
68 /*
69 * TODO: Consider the possibility of specifying the SPSR in
70 * the FIP ToC and allowing the platform to have a say as
71 * well.
72 */
73 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
74 return spsr;
75}
Soby Mathew0d268dc2016-07-11 14:13:56 +010076#else
77/*******************************************************************************
78 * Gets SPSR for BL33 entry
79 ******************************************************************************/
80uint32_t arm_get_spsr_for_bl33_entry(void)
81{
82 unsigned int hyp_status, mode, spsr;
83
84 hyp_status = GET_VIRT_EXT(read_id_pfr1());
85
86 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
87
88 /*
89 * TODO: Consider the possibility of specifying the SPSR in
90 * the FIP ToC and allowing the platform to have a say as
91 * well.
92 */
93 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
94 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
95 return spsr;
96}
97#endif /* AARCH32 */
Dan Handley9df48042015-03-19 18:58:55 +000098
Soby Mathew61e8d0b2015-10-12 17:32:29 +010099/*******************************************************************************
100 * Configures access to the system counter timer module.
101 ******************************************************************************/
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800102#ifdef ARM_SYS_TIMCTL_BASE
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100103void arm_configure_sys_timer(void)
104{
105 unsigned int reg_val;
106
Soby Mathew2d9f7952018-06-11 16:21:30 +0100107 /* Read the frequency of the system counter */
108 unsigned int freq_val = plat_get_syscnt_freq2();
109
Juan Castilloaadf19a2015-11-06 16:02:32 +0000110#if ARM_CONFIG_CNTACR
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000111 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT);
112 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT);
113 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100114 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
Juan Castilloaadf19a2015-11-06 16:02:32 +0000115#endif /* ARM_CONFIG_CNTACR */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100116
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000117 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100118 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
Soby Mathew2d9f7952018-06-11 16:21:30 +0100119
120 /*
121 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ
122 * system register initialized during psci_arch_setup() is different
123 * from this and has to be updated independently.
124 */
125 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
126
127#ifdef PLAT_juno
128 /*
129 * Initialize CNTFRQ register in Non-secure CNTBase frame.
130 * This is only required for Juno, because it doesn't follow ARM ARM
131 * in that the value updated in CNTFRQ is not reflected in CNTBASE_CNTFRQ.
132 * Hence update the value manually.
133 */
134 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASE_CNTFRQ, freq_val);
135#endif
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100136}
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800137#endif /* ARM_SYS_TIMCTL_BASE */
Vikram Kanigiri07035432015-11-12 18:52:34 +0000138
139/*******************************************************************************
140 * Returns ARM platform specific memory map regions.
141 ******************************************************************************/
142const mmap_region_t *plat_arm_get_mmap(void)
143{
144 return plat_arm_mmap;
145}
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100146
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100147#ifdef ARM_SYS_CNTCTL_BASE
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100148
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100149unsigned int plat_get_syscnt_freq2(void)
150{
Sandrine Bailleuxa8ef6652016-06-03 15:00:46 +0100151 unsigned int counter_base_frequency;
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100152
153 /* Read the frequency from Frequency modes table */
154 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
155
156 /* The first entry of the frequency modes table must not be 0 */
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000157 if (counter_base_frequency == 0U)
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100158 panic();
159
160 return counter_base_frequency;
161}
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100162
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100163#endif /* ARM_SYS_CNTCTL_BASE */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100164
165#if SDEI_SUPPORT
166/*
167 * Translate SDEI entry point to PA, and perform standard ARM entry point
168 * validation on it.
169 */
170int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode)
171{
172 uint64_t par, pa;
173 uint32_t scr_el3;
174
175 /* Doing Non-secure address translation requires SCR_EL3.NS set */
176 scr_el3 = read_scr_el3();
177 write_scr_el3(scr_el3 | SCR_NS_BIT);
178 isb();
179
180 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1));
181 if (client_mode == MODE_EL2) {
182 /*
183 * Translate entry point to Physical Address using the EL2
184 * translation regime.
185 */
186 ats1e2r(ep);
187 } else {
188 /*
189 * Translate entry point to Physical Address using the EL1&0
190 * translation regime, including stage 2.
191 */
192 ats12e1r(ep);
193 }
194 isb();
195 par = read_par_el1();
196
197 /* Restore original SCRL_EL3 */
198 write_scr_el3(scr_el3);
199 isb();
200
201 /* If the translation resulted in fault, return failure */
202 if ((par & PAR_F_MASK) != 0)
203 return -1;
204
205 /* Extract Physical Address from PAR */
206 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT));
207
208 /* Perform NS entry point validation on the physical address */
209 return arm_validate_ns_entrypoint(pa);
210}
211#endif