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Varun Wadekarecd6a5a2018-04-09 17:48:58 -07001/*
Varun Wadekar2909fa32020-01-09 08:52:10 -08002 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Varun Wadekar2909fa32020-01-09 08:52:10 -08007#ifndef TEGRA_DEF_H
8#define TEGRA_DEF_H
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07009
10#include <lib/utils_def.h>
11
12/*******************************************************************************
Steven Kao0e6dce62018-02-09 21:01:49 +080013 * Chip specific page table and MMU setup constants
14 ******************************************************************************/
15#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
16#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40)
17
18/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070019 * These values are used by the PSCI implementation during the `CPU_SUSPEND`
20 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
21 * parameter.
22 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080023#define PSTATE_ID_CORE_IDLE U(6)
24#define PSTATE_ID_CORE_POWERDN U(7)
25#define PSTATE_ID_SOC_POWERDN U(2)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070026
27/*******************************************************************************
28 * Platform power states (used by PSCI framework)
29 *
30 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
31 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
32 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080033#define PLAT_MAX_RET_STATE U(1)
34#define PLAT_MAX_OFF_STATE U(8)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070035
36/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070037 * Secure IRQ definitions
38 ******************************************************************************/
Varun Wadekar362a6b22017-11-10 11:04:42 -080039#define TEGRA194_MAX_SEC_IRQS U(2)
40#define TEGRA194_TOP_WDT_IRQ U(49)
41#define TEGRA194_AON_WDT_IRQ U(50)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070042
Varun Wadekar362a6b22017-11-10 11:04:42 -080043#define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070044
45/*******************************************************************************
Varun Wadekare55c27b2018-09-13 08:47:43 -070046 * Clock identifier for the SE device
47 ******************************************************************************/
48#define TEGRA194_CLK_SE U(124)
49#define TEGRA_CLK_SE TEGRA194_CLK_SE
50
51/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070052 * Tegra Miscellanous register constants
53 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080054#define TEGRA_MISC_BASE U(0x00100000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070055
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080056#define HARDWARE_REVISION_OFFSET U(0x4)
57#define MISCREG_EMU_REVID U(0x3160)
58#define BOARD_MASK_BITS U(0xFF)
59#define BOARD_SHIFT_BITS U(24)
60#define MISCREG_PFCFG U(0x200C)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070061
62/*******************************************************************************
Varun Wadekar602cf7e2018-04-03 13:10:48 -070063 * Tegra General Purpose Centralised DMA constants
64 ******************************************************************************/
65#define TEGRA_GPCDMA_BASE U(0x02610000)
66
67/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070068 * Tegra Memory Controller constants
69 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080070#define TEGRA_MC_STREAMID_BASE U(0x02C00000)
71#define TEGRA_MC_BASE U(0x02C10000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070072
Varun Wadekar07897a92017-02-13 09:00:04 -080073/* General Security Carveout register macros */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080074#define MC_GSC_CONFIG_REGS_SIZE U(0x40)
75#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
76#define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0)
77#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
78#define MC_GSC_BASE_LO_SHIFT U(12)
79#define MC_GSC_BASE_LO_MASK U(0xFFFFF)
80#define MC_GSC_BASE_HI_SHIFT U(0)
81#define MC_GSC_BASE_HI_MASK U(3)
Varun Wadekar4309d7b2017-10-03 15:25:44 -070082#define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31)
Varun Wadekar07897a92017-02-13 09:00:04 -080083
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070084/* TZDRAM carveout configuration registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080085#define MC_SECURITY_CFG0_0 U(0x70)
86#define MC_SECURITY_CFG1_0 U(0x74)
87#define MC_SECURITY_CFG3_0 U(0x9BC)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070088
Harvey Hsieh53fc0322017-08-09 16:26:33 +080089#define MC_SECURITY_BOM_MASK (U(0xFFF) << 20)
90#define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0)
91#define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0)
92
Steven Kaoee93ed12017-11-14 19:12:58 +080093#define MC_SECURITY_CFG_REG_CTRL_0 U(0x154)
94#define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0)
Steven Kaob2b43052017-11-30 11:53:29 +080095#define SECURITY_CFG_WRITE_ACCESS_ENABLE U(0x0)
96#define SECURITY_CFG_WRITE_ACCESS_DISABLE U(0x1)
Steven Kaoee93ed12017-11-14 19:12:58 +080097
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070098/* Video Memory carveout configuration registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080099#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
100#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
101#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700102
Varun Wadekar07897a92017-02-13 09:00:04 -0800103/*
104 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
105 * non-overlapping Video memory region
106 */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800107#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
108#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
109#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
110#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
111#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
Varun Wadekar07897a92017-02-13 09:00:04 -0800112
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700113/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800114#define MC_TZRAM_CARVEOUT_CFG U(0x2190)
115#define MC_TZRAM_BASE_LO U(0x2194)
116#define MC_TZRAM_BASE_HI U(0x2198)
117#define MC_TZRAM_SIZE U(0x219C)
Varun Wadekar4309d7b2017-10-03 15:25:44 -0700118#define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0)
119#define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4)
120#define TZRAM_ALLOW_MPCORER (U(1) << 7)
121#define TZRAM_ALLOW_MPCOREW (U(1) << 25)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700122
123/* Memory Controller Reset Control registers */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800124#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28)
125#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29)
126#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30)
127#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700128
129/*******************************************************************************
130 * Tegra UART Controller constants
131 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800132#define TEGRA_UARTA_BASE U(0x03100000)
133#define TEGRA_UARTB_BASE U(0x03110000)
134#define TEGRA_UARTC_BASE U(0x0C280000)
135#define TEGRA_UARTD_BASE U(0x03130000)
136#define TEGRA_UARTE_BASE U(0x03140000)
137#define TEGRA_UARTF_BASE U(0x03150000)
138#define TEGRA_UARTG_BASE U(0x0C290000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700139
140/*******************************************************************************
Varun Wadekar03aa0142018-01-23 14:51:40 -0800141 * XUSB PADCTL
142 ******************************************************************************/
143#define TEGRA_XUSB_PADCTL_BASE U(0x03520000)
144#define TEGRA_XUSB_PADCTL_SIZE U(0x10000)
145#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c)
146#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370)
147#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374)
148#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378)
149#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c)
150#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c)
151
152/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700153 * Tegra Fuse Controller related constants
154 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800155#define TEGRA_FUSE_BASE U(0x03820000)
156#define OPT_SUBREVISION U(0x248)
157#define SUBREVISION_MASK U(0xF)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700158
159/*******************************************************************************
160 * GICv2 & interrupt handling related constants
161 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800162#define TEGRA_GICD_BASE U(0x03881000)
163#define TEGRA_GICC_BASE U(0x03882000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700164
165/*******************************************************************************
166 * Security Engine related constants
167 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800168#define TEGRA_SE0_BASE U(0x03AC0000)
Steven Kao530b2172017-06-23 16:18:58 +0800169#define SE0_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
170#define SE0_AES0_ENTROPY_SRC_AGE_CTRL U(0x2FC)
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800171#define TEGRA_PKA1_BASE U(0x03AD0000)
Steven Kao530b2172017-06-23 16:18:58 +0800172#define SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144)
173#define PKA1_MUTEX_WATCHDOG_NS_LIMIT SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800174#define TEGRA_RNG1_BASE U(0x03AE0000)
Steven Kao530b2172017-06-23 16:18:58 +0800175#define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700176
177/*******************************************************************************
steven kaoe5796062018-01-02 19:09:04 -0800178 * Tegra HSP doorbell #0 constants
179 ******************************************************************************/
Varun Wadekar03aa0142018-01-23 14:51:40 -0800180#define TEGRA_HSP_DBELL_BASE U(0x03C90000)
181#define HSP_DBELL_1_ENABLE U(0x104)
182#define HSP_DBELL_3_TRIGGER U(0x300)
183#define HSP_DBELL_3_ENABLE U(0x304)
steven kaoe5796062018-01-02 19:09:04 -0800184
185/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700186 * Tegra hardware synchronization primitives for the SPE engine
187 ******************************************************************************/
188#define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000)
189#define TEGRA_CONSOLE_SPE_BASE (TEGRA_AON_HSP_SM_6_7_BASE + U(0x8000))
190
191/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700192 * Tegra micro-seconds timer constants
193 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800194#define TEGRA_TMRUS_BASE U(0x0C2E0000)
195#define TEGRA_TMRUS_SIZE U(0x10000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700196
197/*******************************************************************************
198 * Tegra Power Mgmt Controller constants
199 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800200#define TEGRA_PMC_BASE U(0x0C360000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700201
202/*******************************************************************************
203 * Tegra scratch registers constants
204 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800205#define TEGRA_SCRATCH_BASE U(0x0C390000)
Jeetesh Burmandbcc95c2018-07-06 20:03:38 +0530206#define SECURE_SCRATCH_RSV68_LO U(0x284)
207#define SECURE_SCRATCH_RSV68_HI U(0x288)
208#define SECURE_SCRATCH_RSV69_LO U(0x28C)
209#define SECURE_SCRATCH_RSV69_HI U(0x290)
210#define SECURE_SCRATCH_RSV70_LO U(0x294)
211#define SECURE_SCRATCH_RSV70_HI U(0x298)
212#define SECURE_SCRATCH_RSV71_LO U(0x29C)
213#define SECURE_SCRATCH_RSV71_HI U(0x2A0)
Jeetesh Burman254b57d2018-07-06 19:58:30 +0530214#define SECURE_SCRATCH_RSV72_LO U(0x2A4)
215#define SECURE_SCRATCH_RSV72_HI U(0x2A8)
Steven Kao08ac2732018-02-09 21:35:20 +0800216#define SECURE_SCRATCH_RSV75 U(0x2BC)
steven kao150d0332017-12-23 17:58:58 -0800217#define SECURE_SCRATCH_RSV81_LO U(0x2EC)
218#define SECURE_SCRATCH_RSV81_HI U(0x2F0)
Steven Kao4607f172017-10-23 18:35:14 +0800219#define SECURE_SCRATCH_RSV97 U(0x36C)
220#define SECURE_SCRATCH_RSV99_LO U(0x37C)
221#define SECURE_SCRATCH_RSV99_HI U(0x380)
222#define SECURE_SCRATCH_RSV109_LO U(0x3CC)
223#define SECURE_SCRATCH_RSV109_HI U(0x3D0)
224
Steven Kao08ac2732018-02-09 21:35:20 +0800225#define SCRATCH_BL31_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75
226#define SCRATCH_BL31_PARAMS_HI_ADDR_MASK U(0xFFFF)
227#define SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT U(0)
228#define SCRATCH_BL31_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_LO
229#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75
230#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK U(0xFFFF0000)
231#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16)
232#define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI
Steven Kao4607f172017-10-23 18:35:14 +0800233#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97
Pritesh Raithatha75c94432018-08-03 15:48:15 +0530234#define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO
235#define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI
Steven Kao4607f172017-10-23 18:35:14 +0800236#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO
237#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700238
239/*******************************************************************************
240 * Tegra Memory Mapped Control Register Access Bus constants
241 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800242#define TEGRA_MMCRAB_BASE U(0x0E000000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700243
244/*******************************************************************************
245 * Tegra SMMU Controller constants
246 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800247#define TEGRA_SMMU0_BASE U(0x12000000)
248#define TEGRA_SMMU1_BASE U(0x11000000)
249#define TEGRA_SMMU2_BASE U(0x10000000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700250
251/*******************************************************************************
252 * Tegra TZRAM constants
253 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800254#define TEGRA_TZRAM_BASE U(0x40000000)
255#define TEGRA_TZRAM_SIZE U(0x40000)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700256
257/*******************************************************************************
steven kaoe5796062018-01-02 19:09:04 -0800258 * Tegra CCPLEX-BPMP IPC constants
259 ******************************************************************************/
260#define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x4004C000)
261#define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x4004D000)
262#define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */
263
264/*******************************************************************************
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700265 * Tegra Clock and Reset Controller constants
266 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800267#define TEGRA_CAR_RESET_BASE U(0x20000000)
Jeetesh Burman0f174f12018-01-22 16:52:11 +0530268#define TEGRA_GPU_RESET_REG_OFFSET U(0x18)
269#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C)
270#define GPU_RESET_BIT (U(1) << 0)
271#define GPU_SET_BIT (U(1) << 0)
Varun Wadekar602cf7e2018-04-03 13:10:48 -0700272#define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004)
273#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700274
Varun Wadekar00759902017-05-31 11:41:00 -0700275/*******************************************************************************
Varun Wadekar1b0c1242018-05-15 11:24:59 -0700276 * Tegra DRAM memory base address
277 ******************************************************************************/
278#define TEGRA_DRAM_BASE ULL(0x80000000)
279#define TEGRA_DRAM_END ULL(0xFFFFFFFFF)
280
281/*******************************************************************************
Ajay Gupta81621092017-08-01 15:53:04 -0700282 * XUSB STREAMIDs
283 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800284#define TEGRA_SID_XUSB_HOST U(0x1b)
285#define TEGRA_SID_XUSB_DEV U(0x1c)
286#define TEGRA_SID_XUSB_VF0 U(0x5d)
287#define TEGRA_SID_XUSB_VF1 U(0x5e)
288#define TEGRA_SID_XUSB_VF2 U(0x5f)
289#define TEGRA_SID_XUSB_VF3 U(0x60)
Ajay Gupta81621092017-08-01 15:53:04 -0700290
Varun Wadekar2909fa32020-01-09 08:52:10 -0800291#endif /* TEGRA_DEF_H */