Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 6 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 7 | #include <asm_macros.S> |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 8 | #include <assert_macros.S> |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 9 | #include <bl_common.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 10 | #include <cortex_a57.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 11 | #include <cpu_macros.S> |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 12 | #include <debug.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 13 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 14 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 15 | /* --------------------------------------------- |
| 16 | * Disable L1 data cache and unified L2 cache |
| 17 | * --------------------------------------------- |
| 18 | */ |
| 19 | func cortex_a57_disable_dcache |
| 20 | mrs x1, sctlr_el3 |
| 21 | bic x1, x1, #SCTLR_C_BIT |
| 22 | msr sctlr_el3, x1 |
| 23 | isb |
| 24 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 25 | endfunc cortex_a57_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 26 | |
| 27 | /* --------------------------------------------- |
| 28 | * Disable all types of L2 prefetches. |
| 29 | * --------------------------------------------- |
| 30 | */ |
| 31 | func cortex_a57_disable_l2_prefetch |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 32 | mrs x0, CORTEX_A57_ECTLR_EL1 |
| 33 | orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 34 | mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK |
| 35 | orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 36 | bic x0, x0, x1 |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 37 | msr CORTEX_A57_ECTLR_EL1, x0 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 38 | isb |
Soby Mathew | 1604fa0 | 2014-09-22 12:15:26 +0100 | [diff] [blame] | 39 | dsb ish |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 40 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 41 | endfunc cortex_a57_disable_l2_prefetch |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 42 | |
| 43 | /* --------------------------------------------- |
| 44 | * Disable intra-cluster coherency |
| 45 | * --------------------------------------------- |
| 46 | */ |
| 47 | func cortex_a57_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 48 | mrs x0, CORTEX_A57_ECTLR_EL1 |
| 49 | bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT |
| 50 | msr CORTEX_A57_ECTLR_EL1, x0 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 51 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 52 | endfunc cortex_a57_disable_smp |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 53 | |
| 54 | /* --------------------------------------------- |
| 55 | * Disable debug interfaces |
| 56 | * --------------------------------------------- |
| 57 | */ |
| 58 | func cortex_a57_disable_ext_debug |
| 59 | mov x0, #1 |
| 60 | msr osdlr_el1, x0 |
| 61 | isb |
| 62 | dsb sy |
| 63 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 64 | endfunc cortex_a57_disable_ext_debug |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 65 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 66 | /* -------------------------------------------------- |
| 67 | * Errata Workaround for Cortex A57 Errata #806969. |
| 68 | * This applies only to revision r0p0 of Cortex A57. |
| 69 | * Inputs: |
| 70 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 71 | * Shall clobber: x0-x17 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 72 | * -------------------------------------------------- |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 73 | */ |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 74 | func errata_a57_806969_wa |
| 75 | /* |
| 76 | * Compare x0 against revision r0p0 |
| 77 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 78 | mov x17, x30 |
| 79 | bl check_errata_806969 |
| 80 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 81 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 82 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA |
| 83 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 84 | 1: |
| 85 | ret x17 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 86 | endfunc errata_a57_806969_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 87 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 88 | func check_errata_806969 |
| 89 | mov x1, #0x00 |
| 90 | b cpu_rev_var_ls |
| 91 | endfunc check_errata_806969 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 92 | |
| 93 | /* --------------------------------------------------- |
Antonio Nino Diaz | 3f13c35 | 2017-02-24 11:39:22 +0000 | [diff] [blame] | 94 | * Errata Workaround for Cortex A57 Errata #813419. |
| 95 | * This applies only to revision r0p0 of Cortex A57. |
| 96 | * --------------------------------------------------- |
| 97 | */ |
| 98 | func check_errata_813419 |
| 99 | /* |
| 100 | * Even though this is only needed for revision r0p0, it |
| 101 | * is always applied due to limitations of the current |
| 102 | * errata framework. |
| 103 | */ |
| 104 | mov x0, #ERRATA_APPLIES |
| 105 | ret |
| 106 | endfunc check_errata_813419 |
| 107 | |
| 108 | /* --------------------------------------------------- |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 109 | * Errata Workaround for Cortex A57 Errata #813420. |
| 110 | * This applies only to revision r0p0 of Cortex A57. |
| 111 | * Inputs: |
| 112 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 113 | * Shall clobber: x0-x17 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 114 | * --------------------------------------------------- |
| 115 | */ |
| 116 | func errata_a57_813420_wa |
| 117 | /* |
| 118 | * Compare x0 against revision r0p0 |
| 119 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 120 | mov x17, x30 |
| 121 | bl check_errata_813420 |
| 122 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 123 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 124 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI |
| 125 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 126 | 1: |
| 127 | ret x17 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 128 | endfunc errata_a57_813420_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 129 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 130 | func check_errata_813420 |
| 131 | mov x1, #0x00 |
| 132 | b cpu_rev_var_ls |
| 133 | endfunc check_errata_813420 |
| 134 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 135 | /* -------------------------------------------------------------------- |
| 136 | * Disable the over-read from the LDNP instruction. |
| 137 | * |
| 138 | * This applies to all revisions <= r1p2. The performance degradation |
| 139 | * observed with LDNP/STNP has been fixed on r1p3 and onwards. |
| 140 | * |
| 141 | * Inputs: |
| 142 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 143 | * Shall clobber: x0-x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 144 | * --------------------------------------------------------------------- |
| 145 | */ |
| 146 | func a57_disable_ldnp_overread |
| 147 | /* |
| 148 | * Compare x0 against revision r1p2 |
| 149 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 150 | mov x17, x30 |
| 151 | bl check_errata_disable_ldnp_overread |
| 152 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 153 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 154 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD |
| 155 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 156 | 1: |
| 157 | ret x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 158 | endfunc a57_disable_ldnp_overread |
| 159 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 160 | func check_errata_disable_ldnp_overread |
| 161 | mov x1, #0x12 |
| 162 | b cpu_rev_var_ls |
| 163 | endfunc check_errata_disable_ldnp_overread |
| 164 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 165 | /* --------------------------------------------------- |
| 166 | * Errata Workaround for Cortex A57 Errata #826974. |
| 167 | * This applies only to revision <= r1p1 of Cortex A57. |
| 168 | * Inputs: |
| 169 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 170 | * Shall clobber: x0-x17 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 171 | * --------------------------------------------------- |
| 172 | */ |
| 173 | func errata_a57_826974_wa |
| 174 | /* |
| 175 | * Compare x0 against revision r1p1 |
| 176 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 177 | mov x17, x30 |
| 178 | bl check_errata_826974 |
| 179 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 180 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 181 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB |
| 182 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 183 | 1: |
| 184 | ret x17 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 185 | endfunc errata_a57_826974_wa |
| 186 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 187 | func check_errata_826974 |
| 188 | mov x1, #0x11 |
| 189 | b cpu_rev_var_ls |
| 190 | endfunc check_errata_826974 |
| 191 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 192 | /* --------------------------------------------------- |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 193 | * Errata Workaround for Cortex A57 Errata #826977. |
| 194 | * This applies only to revision <= r1p1 of Cortex A57. |
| 195 | * Inputs: |
| 196 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 197 | * Shall clobber: x0-x17 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 198 | * --------------------------------------------------- |
| 199 | */ |
| 200 | func errata_a57_826977_wa |
| 201 | /* |
| 202 | * Compare x0 against revision r1p1 |
| 203 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 204 | mov x17, x30 |
| 205 | bl check_errata_826977 |
| 206 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 207 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 208 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE |
| 209 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 210 | 1: |
| 211 | ret x17 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 212 | endfunc errata_a57_826977_wa |
| 213 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 214 | func check_errata_826977 |
| 215 | mov x1, #0x11 |
| 216 | b cpu_rev_var_ls |
| 217 | endfunc check_errata_826977 |
| 218 | |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 219 | /* --------------------------------------------------- |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 220 | * Errata Workaround for Cortex A57 Errata #828024. |
| 221 | * This applies only to revision <= r1p1 of Cortex A57. |
| 222 | * Inputs: |
| 223 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 224 | * Shall clobber: x0-x17 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 225 | * --------------------------------------------------- |
| 226 | */ |
| 227 | func errata_a57_828024_wa |
| 228 | /* |
| 229 | * Compare x0 against revision r1p1 |
| 230 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 231 | mov x17, x30 |
| 232 | bl check_errata_828024 |
| 233 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 234 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 235 | /* |
| 236 | * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 |
| 237 | * instructions here because the resulting bitmask doesn't fit in a |
| 238 | * 16-bit value so it cannot be encoded in a single instruction. |
| 239 | */ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 240 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA |
| 241 | orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \ |
| 242 | CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING) |
| 243 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 244 | 1: |
| 245 | ret x17 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 246 | endfunc errata_a57_828024_wa |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 247 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 248 | func check_errata_828024 |
| 249 | mov x1, #0x11 |
| 250 | b cpu_rev_var_ls |
| 251 | endfunc check_errata_828024 |
| 252 | |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 253 | /* --------------------------------------------------- |
| 254 | * Errata Workaround for Cortex A57 Errata #829520. |
| 255 | * This applies only to revision <= r1p2 of Cortex A57. |
| 256 | * Inputs: |
| 257 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 258 | * Shall clobber: x0-x17 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 259 | * --------------------------------------------------- |
| 260 | */ |
| 261 | func errata_a57_829520_wa |
| 262 | /* |
| 263 | * Compare x0 against revision r1p2 |
| 264 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 265 | mov x17, x30 |
| 266 | bl check_errata_829520 |
| 267 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 268 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 269 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR |
| 270 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 271 | 1: |
| 272 | ret x17 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 273 | endfunc errata_a57_829520_wa |
| 274 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 275 | func check_errata_829520 |
| 276 | mov x1, #0x12 |
| 277 | b cpu_rev_var_ls |
| 278 | endfunc check_errata_829520 |
| 279 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 280 | /* --------------------------------------------------- |
| 281 | * Errata Workaround for Cortex A57 Errata #833471. |
| 282 | * This applies only to revision <= r1p2 of Cortex A57. |
| 283 | * Inputs: |
| 284 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 285 | * Shall clobber: x0-x17 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 286 | * --------------------------------------------------- |
| 287 | */ |
| 288 | func errata_a57_833471_wa |
| 289 | /* |
| 290 | * Compare x0 against revision r1p2 |
| 291 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 292 | mov x17, x30 |
| 293 | bl check_errata_833471 |
| 294 | cbz x0, 1f |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 295 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 296 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH |
| 297 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 298 | 1: |
| 299 | ret x17 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 300 | endfunc errata_a57_833471_wa |
| 301 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 302 | func check_errata_833471 |
| 303 | mov x1, #0x12 |
| 304 | b cpu_rev_var_ls |
| 305 | endfunc check_errata_833471 |
| 306 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 307 | /* -------------------------------------------------- |
| 308 | * Errata Workaround for Cortex A57 Errata #859972. |
| 309 | * This applies only to revision <= r1p3 of Cortex A57. |
| 310 | * Inputs: |
| 311 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 312 | * Shall clobber: |
| 313 | * -------------------------------------------------- |
| 314 | */ |
| 315 | func errata_a57_859972_wa |
| 316 | mov x17, x30 |
| 317 | bl check_errata_859972 |
| 318 | cbz x0, 1f |
| 319 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
| 320 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH |
| 321 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
| 322 | 1: |
| 323 | ret x17 |
| 324 | endfunc errata_a57_859972_wa |
| 325 | |
| 326 | func check_errata_859972 |
| 327 | mov x1, #0x13 |
| 328 | b cpu_rev_var_ls |
| 329 | endfunc check_errata_859972 |
| 330 | |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 331 | func check_errata_cve_2017_5715 |
| 332 | #if WORKAROUND_CVE_2017_5715 |
| 333 | mov x0, #ERRATA_APPLIES |
| 334 | #else |
| 335 | mov x0, #ERRATA_MISSING |
| 336 | #endif |
| 337 | ret |
| 338 | endfunc check_errata_cve_2017_5715 |
| 339 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 340 | /* ------------------------------------------------- |
| 341 | * The CPU Ops reset function for Cortex-A57. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 342 | * Shall clobber: x0-x19 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 343 | * ------------------------------------------------- |
| 344 | */ |
| 345 | func cortex_a57_reset_func |
| 346 | mov x19, x30 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 347 | bl cpu_get_rev_var |
| 348 | mov x18, x0 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 349 | |
| 350 | #if ERRATA_A57_806969 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 351 | mov x0, x18 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 352 | bl errata_a57_806969_wa |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 353 | #endif |
| 354 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 355 | #if ERRATA_A57_813420 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 356 | mov x0, x18 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 357 | bl errata_a57_813420_wa |
| 358 | #endif |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 359 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 360 | #if A57_DISABLE_NON_TEMPORAL_HINT |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 361 | mov x0, x18 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 362 | bl a57_disable_ldnp_overread |
| 363 | #endif |
| 364 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 365 | #if ERRATA_A57_826974 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 366 | mov x0, x18 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 367 | bl errata_a57_826974_wa |
| 368 | #endif |
| 369 | |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 370 | #if ERRATA_A57_826977 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 371 | mov x0, x18 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 372 | bl errata_a57_826977_wa |
| 373 | #endif |
| 374 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 375 | #if ERRATA_A57_828024 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 376 | mov x0, x18 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 377 | bl errata_a57_828024_wa |
| 378 | #endif |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 379 | |
| 380 | #if ERRATA_A57_829520 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 381 | mov x0, x18 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 382 | bl errata_a57_829520_wa |
| 383 | #endif |
| 384 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 385 | #if ERRATA_A57_833471 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 386 | mov x0, x18 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 387 | bl errata_a57_833471_wa |
| 388 | #endif |
| 389 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 390 | #if ERRATA_A57_859972 |
| 391 | mov x0, x18 |
| 392 | bl errata_a57_859972_wa |
| 393 | #endif |
| 394 | |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 395 | #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 |
| 396 | adr x0, workaround_mmu_runtime_exceptions |
| 397 | msr vbar_el3, x0 |
| 398 | #endif |
| 399 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 400 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 401 | * Enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 402 | * --------------------------------------------- |
| 403 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 404 | mrs x0, CORTEX_A57_ECTLR_EL1 |
| 405 | orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT |
| 406 | msr CORTEX_A57_ECTLR_EL1, x0 |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 407 | isb |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 408 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 409 | endfunc cortex_a57_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 410 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 411 | /* ---------------------------------------------------- |
| 412 | * The CPU Ops core power down function for Cortex-A57. |
| 413 | * ---------------------------------------------------- |
| 414 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 415 | func cortex_a57_core_pwr_dwn |
| 416 | mov x18, x30 |
| 417 | |
| 418 | /* --------------------------------------------- |
| 419 | * Turn off caches. |
| 420 | * --------------------------------------------- |
| 421 | */ |
| 422 | bl cortex_a57_disable_dcache |
| 423 | |
| 424 | /* --------------------------------------------- |
| 425 | * Disable the L2 prefetches. |
| 426 | * --------------------------------------------- |
| 427 | */ |
| 428 | bl cortex_a57_disable_l2_prefetch |
| 429 | |
| 430 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 431 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 432 | * --------------------------------------------- |
| 433 | */ |
| 434 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 435 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 436 | |
| 437 | /* --------------------------------------------- |
| 438 | * Come out of intra cluster coherency |
| 439 | * --------------------------------------------- |
| 440 | */ |
| 441 | bl cortex_a57_disable_smp |
| 442 | |
| 443 | /* --------------------------------------------- |
| 444 | * Force the debug interfaces to be quiescent |
| 445 | * --------------------------------------------- |
| 446 | */ |
| 447 | mov x30, x18 |
| 448 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 449 | endfunc cortex_a57_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 450 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 451 | /* ------------------------------------------------------- |
| 452 | * The CPU Ops cluster power down function for Cortex-A57. |
| 453 | * ------------------------------------------------------- |
| 454 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 455 | func cortex_a57_cluster_pwr_dwn |
| 456 | mov x18, x30 |
| 457 | |
| 458 | /* --------------------------------------------- |
| 459 | * Turn off caches. |
| 460 | * --------------------------------------------- |
| 461 | */ |
| 462 | bl cortex_a57_disable_dcache |
| 463 | |
| 464 | /* --------------------------------------------- |
| 465 | * Disable the L2 prefetches. |
| 466 | * --------------------------------------------- |
| 467 | */ |
| 468 | bl cortex_a57_disable_l2_prefetch |
| 469 | |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 470 | #if !SKIP_A57_L1_FLUSH_PWR_DWN |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 471 | /* ------------------------------------------------- |
| 472 | * Flush the L1 caches. |
| 473 | * ------------------------------------------------- |
| 474 | */ |
| 475 | mov x0, #DCCISW |
| 476 | bl dcsw_op_level1 |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 477 | #endif |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 478 | /* --------------------------------------------- |
| 479 | * Disable the optional ACP. |
| 480 | * --------------------------------------------- |
| 481 | */ |
| 482 | bl plat_disable_acp |
| 483 | |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 484 | /* ------------------------------------------------- |
| 485 | * Flush the L2 caches. |
| 486 | * ------------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 487 | */ |
| 488 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 489 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 490 | |
| 491 | /* --------------------------------------------- |
| 492 | * Come out of intra cluster coherency |
| 493 | * --------------------------------------------- |
| 494 | */ |
| 495 | bl cortex_a57_disable_smp |
| 496 | |
| 497 | /* --------------------------------------------- |
| 498 | * Force the debug interfaces to be quiescent |
| 499 | * --------------------------------------------- |
| 500 | */ |
| 501 | mov x30, x18 |
| 502 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 503 | endfunc cortex_a57_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 504 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 505 | #if REPORT_ERRATA |
| 506 | /* |
| 507 | * Errata printing function for Cortex A57. Must follow AAPCS. |
| 508 | */ |
| 509 | func cortex_a57_errata_report |
| 510 | stp x8, x30, [sp, #-16]! |
| 511 | |
| 512 | bl cpu_get_rev_var |
| 513 | mov x8, x0 |
| 514 | |
| 515 | /* |
| 516 | * Report all errata. The revision-variant information is passed to |
| 517 | * checking functions of each errata. |
| 518 | */ |
| 519 | report_errata ERRATA_A57_806969, cortex_a57, 806969 |
Antonio Nino Diaz | 3f13c35 | 2017-02-24 11:39:22 +0000 | [diff] [blame] | 520 | report_errata ERRATA_A57_813419, cortex_a57, 813419 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 521 | report_errata ERRATA_A57_813420, cortex_a57, 813420 |
| 522 | report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ |
| 523 | disable_ldnp_overread |
| 524 | report_errata ERRATA_A57_826974, cortex_a57, 826974 |
| 525 | report_errata ERRATA_A57_826977, cortex_a57, 826977 |
| 526 | report_errata ERRATA_A57_828024, cortex_a57, 828024 |
| 527 | report_errata ERRATA_A57_829520, cortex_a57, 829520 |
| 528 | report_errata ERRATA_A57_833471, cortex_a57, 833471 |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 529 | report_errata ERRATA_A57_859972, cortex_a57, 859972 |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 530 | report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 531 | |
| 532 | ldp x8, x30, [sp], #16 |
| 533 | ret |
| 534 | endfunc cortex_a57_errata_report |
| 535 | #endif |
| 536 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 537 | /* --------------------------------------------- |
| 538 | * This function provides cortex_a57 specific |
| 539 | * register information for crash reporting. |
| 540 | * It needs to return with x6 pointing to |
| 541 | * a list of register names in ascii and |
| 542 | * x8 - x15 having values of registers to be |
| 543 | * reported. |
| 544 | * --------------------------------------------- |
| 545 | */ |
| 546 | .section .rodata.cortex_a57_regs, "aS" |
| 547 | cortex_a57_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 548 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 549 | |
| 550 | func cortex_a57_cpu_reg_dump |
| 551 | adr x6, cortex_a57_regs |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 552 | mrs x8, CORTEX_A57_ECTLR_EL1 |
| 553 | mrs x9, CORTEX_A57_MERRSR_EL1 |
| 554 | mrs x10, CORTEX_A57_L2MERRSR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 555 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 556 | endfunc cortex_a57_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 557 | |
| 558 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 559 | declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ |
| 560 | cortex_a57_reset_func, \ |
| 561 | cortex_a57_core_pwr_dwn, \ |
| 562 | cortex_a57_cluster_pwr_dwn |