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git01.mediatek.com / filogic / atf / 6e84add409b040c0e477f67b41f330fd9d8d8fd5 / . / plat / nvidia / tegra / soc / t194 / platform_t194.mk
blob: a183d0e9daed8737b7103c19e13fea4ff0e3bc4c [file] [log] [blame]
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]1#
Chris Kaye9272152021-09-28 15:52:14 +0100[diff] [blame]2# Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Chris Kaye9272152021-09-28 15:52:14 +0100[diff] [blame]7include common/fdt_wrappers.mk
8
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]9# platform configs
Varun Wadekar19ecdb92017-12-01 09:24:12 -0800[diff] [blame]10ENABLE_CONSOLE_SPE := 1
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]11$(eval $(call add_define,ENABLE_CONSOLE_SPE))
12
Varun Wadekar602cf7e2018-04-03 13:10:48 -0700[diff] [blame]13ENABLE_STRICT_CHECKING_MODE := 1
Steven Kao8f4f1022017-12-13 06:39:15 +0800[diff] [blame]14$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE))
15
Varun Wadekar602cf7e2018-04-03 13:10:48 -0700[diff] [blame]16USE_GPC_DMA := 1
17$(eval $(call add_define,USE_GPC_DMA))
18
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]19RESET_TO_BL31 := 1
20
21PROGRAMMABLE_RESET_ADDRESS := 1
22
23COLD_BOOT_SINGLE_CPU := 1
24
25# platform settings
26TZDRAM_BASE := 0x40000000
27$(eval $(call add_define,TZDRAM_BASE))
28
Ajay Gupta81621092017-08-01 15:53:04 -0700[diff] [blame]29MAX_XLAT_TABLES := 25
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]30$(eval $(call add_define,MAX_XLAT_TABLES))
31
Steven Kao58d11942017-09-29 16:32:34 +0800[diff] [blame]32MAX_MMAP_REGIONS := 30
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]33$(eval $(call add_define,MAX_MMAP_REGIONS))
34
David Pu70f65972019-03-18 15:14:49 -0700[diff] [blame]35# enable RAS handling
Manish Pandey0e3379d2022-10-10 11:43:08 +0100[diff] [blame]36HANDLE_EA_EL3_FIRST_NS := 1
Manish Pandeyd419e222023-02-13 12:39:17 +0000[diff] [blame]37ENABLE_FEAT_RAS := 1
38RAS_FFH_SUPPORT := 1
David Pu70f65972019-03-18 15:14:49 -0700[diff] [blame]39
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]40# platform files
Varun Wadekar26dfb512019-01-17 16:36:23 -0800[diff] [blame]41PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \
42 -I${SOC_DIR}/drivers/include
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]43
Varun Wadekar8b1068b2020-02-26 14:52:01 -0800[diff] [blame]44BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
45 drivers/ti/uart/aarch64/16550_console.S \
Varun Wadekar498d5012017-11-15 15:52:01 -0800[diff] [blame]46 lib/cpus/aarch64/denver.S \
Varun Wadekar0c9105e2019-06-13 15:32:11 -0700[diff] [blame]47 ${TEGRA_DRIVERS}/bpmp_ipc/intf.c \
48 ${TEGRA_DRIVERS}/bpmp_ipc/ivc.c \
49 ${TEGRA_DRIVERS}/memctrl/memctrl_v2.c \
50 ${TEGRA_DRIVERS}/smmu/smmu.c \
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]51 ${SOC_DIR}/drivers/mce/mce.c \
Steven Kao2cdb6782017-01-05 17:04:40 +0800[diff] [blame]52 ${SOC_DIR}/drivers/mce/nvg.c \
53 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
Steven Kao530b2172017-06-23 16:18:58 +0800[diff] [blame]54 ${SOC_DIR}/drivers/se/se.c \
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]55 ${SOC_DIR}/plat_memctrl.c \
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]56 ${SOC_DIR}/plat_psci_handlers.c \
57 ${SOC_DIR}/plat_setup.c \
58 ${SOC_DIR}/plat_secondary.c \
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]59 ${SOC_DIR}/plat_sip_calls.c \
Varun Wadekar362a6b22017-11-10 11:04:42 -0800[diff] [blame]60 ${SOC_DIR}/plat_smmu.c \
61 ${SOC_DIR}/plat_trampoline.S
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]62
Varun Wadekar0c9105e2019-06-13 15:32:11 -0700[diff] [blame]63ifeq (${USE_GPC_DMA}, 1)
64BL31_SOURCES += ${TEGRA_DRIVERS}/gpcdma/gpcdma.c
65endif
66
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]67ifeq (${ENABLE_CONSOLE_SPE},1)
Varun Wadekar0c9105e2019-06-13 15:32:11 -0700[diff] [blame]68BL31_SOURCES += ${TEGRA_DRIVERS}/spe/shared_console.S
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]69endif
David Pu70f65972019-03-18 15:14:49 -0700[diff] [blame]70
71# RAS sources
Manish Pandeyd419e222023-02-13 12:39:17 +0000[diff] [blame]72ifeq (${RAS_FFH_SUPPORT},1)
David Pu70f65972019-03-18 15:14:49 -0700[diff] [blame]73BL31_SOURCES += lib/extensions/ras/std_err_record.c \
74 lib/extensions/ras/ras_common.c \
75 ${SOC_DIR}/plat_ras.c
76endif
Varun Wadekar28d31022020-07-19 21:30:54 -0700[diff] [blame]77
78# SPM dispatcher
79ifeq (${SPD},spmd)
Varun Wadekar28d31022020-07-19 21:30:54 -0700[diff] [blame]80include lib/libfdt/libfdt.mk
81# sources to support spmd
82BL31_SOURCES += plat/common/plat_spmd_manifest.c \
Varun Wadekar28d31022020-07-19 21:30:54 -0700[diff] [blame]83 ${LIBFDT_SRCS}
Chris Kaye9272152021-09-28 15:52:14 +0100[diff] [blame]84
85BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
Varun Wadekar28d31022020-07-19 21:30:54 -0700[diff] [blame]86endif