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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Alexei Fedorov25d7c882020-03-20 18:38:55 +00002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Alexei Fedorov25d7c882020-03-20 18:38:55 +00007#include <assert.h>
8
9#include <bl1/bl1.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
Alexei Fedorov896799a2019-05-09 12:14:40 +010011#include <drivers/arm/smmu_v3.h>
Aditya Angadi20b48412019-04-16 11:29:14 +053012#include <drivers/arm/sp805.h>
Alexei Fedorov896799a2019-05-09 12:14:40 +010013#include <plat/arm/common/arm_config.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000014#include <plat/arm/common/plat_arm.h>
Aditya Angadi20b48412019-04-16 11:29:14 +053015#include <plat/arm/common/arm_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <plat/common/platform.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
19/*******************************************************************************
20 * Perform any BL1 specific platform actions.
21 ******************************************************************************/
22void bl1_early_platform_setup(void)
23{
Dan Handley2b6b5742015-03-19 19:17:53 +000024 arm_bl1_early_platform_setup();
Sandrine Bailleuxe3060e22014-06-13 14:48:18 +010025
Harry Liebel30affd52013-10-30 17:41:48 +000026 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +010027 fvp_config_setup();
James Morrissey9d72b4e2014-02-10 17:04:32 +000028
Dan Handley2b6b5742015-03-19 19:17:53 +000029 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000030 * Initialize Interconnect for this cluster during cold boot.
Dan Handley2b6b5742015-03-19 19:17:53 +000031 * No need for locks as no other CPU is active.
32 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000033 fvp_interconnect_init();
Dan Handley2b6b5742015-03-19 19:17:53 +000034 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000035 * Enable coherency in Interconnect for the primary CPU's cluster.
Dan Handley2b6b5742015-03-19 19:17:53 +000036 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000037 fvp_interconnect_enable();
Vikram Kanigirida567432014-04-15 18:08:08 +010038}
Aditya Angadi20b48412019-04-16 11:29:14 +053039
40void plat_arm_secure_wdt_start(void)
41{
42 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
43}
44
45void plat_arm_secure_wdt_stop(void)
46{
47 sp805_stop(ARM_SP805_TWDG_BASE);
48}
Alexei Fedorov896799a2019-05-09 12:14:40 +010049
50void bl1_platform_setup(void)
51{
52 arm_bl1_platform_setup();
53
Alexei Fedorov7131d832019-08-16 14:15:59 +010054 /* Initialize System level generic or SP804 timer */
55 fvp_timer_init();
56
Alexei Fedorov896799a2019-05-09 12:14:40 +010057 /* On FVP RevC, initialize SMMUv3 */
58 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
59 smmuv3_security_init(PLAT_FVP_SMMUV3_BASE);
60}
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +010061
62__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
63{
64 /* Setup the watchdog to reset the system as soon as possible */
65 sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
66
67 while (1)
68 wfi();
69}
Alexei Fedorov25d7c882020-03-20 18:38:55 +000070
71#if MEASURED_BOOT
72/*
Alexei Fedorov61369a22020-07-13 14:59:02 +010073 * Calculates and writes BL2 hash data to TB_FW_CONFIG DTB.
74 */
75void bl1_plat_set_bl2_hash(const image_desc_t *image_desc)
76{
77 arm_bl1_set_bl2_hash(image_desc);
78}
79
80/*
Alexei Fedorov25d7c882020-03-20 18:38:55 +000081 * Implementation for bl1_plat_handle_post_image_load(). This function
82 * populates the default arguments to BL2. The BL2 memory layout structure
83 * is allocated and the calculated layout is populated in arg1 to BL2.
84 */
85int bl1_plat_handle_post_image_load(unsigned int image_id)
86{
87 meminfo_t *bl2_tzram_layout;
88 meminfo_t *bl1_tzram_layout;
89 image_desc_t *image_desc;
90 entry_point_info_t *ep_info;
91
92 if (image_id != BL2_IMAGE_ID) {
93 return 0;
94 }
95
96 /* Get the image descriptor */
97 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
98 assert(image_desc != NULL);
99
100 /* Calculate BL2 hash and set it in TB_FW_CONFIG */
Alexei Fedorov61369a22020-07-13 14:59:02 +0100101 bl1_plat_set_bl2_hash(image_desc);
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000102
103 /* Get the entry point info */
104 ep_info = &image_desc->ep_info;
105
106 /* Find out how much free trusted ram remains after BL1 load */
107 bl1_tzram_layout = bl1_plat_sec_mem_layout();
108
109 /*
110 * Create a new layout of memory for BL2 as seen by BL1 i.e.
111 * tell it the amount of total and free memory available.
112 * This layout is created at the first free address visible
113 * to BL2. BL2 will read the memory layout before using its
114 * memory for other purposes.
115 */
116 bl2_tzram_layout = (meminfo_t *)bl1_tzram_layout->total_base;
117
118 bl1_calc_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
119
120 ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout;
121
122 VERBOSE("BL1: BL2 memory layout address = %p\n",
123 (void *)bl2_tzram_layout);
124 return 0;
125}
126#endif /* MEASURED_BOOT */