blob: aa567166a1cf239fff424340dc177adfed300bff [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Roberto Vargas2ca18d92018-02-12 12:36:17 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <common/tbbr/tbbr_img_def.h>
Aditya Angadi20b48412019-04-16 11:29:14 +05308#include <drivers/arm/sp805.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +00009#include <plat/arm/common/plat_arm.h>
Aditya Angadi20b48412019-04-16 11:29:14 +053010#include <plat/arm/common/arm_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <plat/common/platform.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010013
14/*******************************************************************************
15 * Perform any BL1 specific platform actions.
16 ******************************************************************************/
17void bl1_early_platform_setup(void)
18{
Dan Handley2b6b5742015-03-19 19:17:53 +000019 arm_bl1_early_platform_setup();
Sandrine Bailleuxe3060e22014-06-13 14:48:18 +010020
Harry Liebel30affd52013-10-30 17:41:48 +000021 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +010022 fvp_config_setup();
James Morrissey9d72b4e2014-02-10 17:04:32 +000023
Dan Handley2b6b5742015-03-19 19:17:53 +000024 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000025 * Initialize Interconnect for this cluster during cold boot.
Dan Handley2b6b5742015-03-19 19:17:53 +000026 * No need for locks as no other CPU is active.
27 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000028 fvp_interconnect_init();
Dan Handley2b6b5742015-03-19 19:17:53 +000029 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000030 * Enable coherency in Interconnect for the primary CPU's cluster.
Dan Handley2b6b5742015-03-19 19:17:53 +000031 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000032 fvp_interconnect_enable();
Vikram Kanigirida567432014-04-15 18:08:08 +010033}
Aditya Angadi20b48412019-04-16 11:29:14 +053034
35void plat_arm_secure_wdt_start(void)
36{
37 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
38}
39
40void plat_arm_secure_wdt_stop(void)
41{
42 sp805_stop(ARM_SP805_TWDG_BASE);
43}