| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
| johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame] | 2 | * Copyright (c) 2022, ARM Limited. All rights reserved. |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CORTEX_A510_H |
| 8 | #define CORTEX_A510_H |
| 9 | |
| 10 | #define CORTEX_A510_MIDR U(0x410FD460) |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * CPU Extended Control register specific definitions |
| 14 | ******************************************************************************/ |
| 15 | #define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 |
| johpow01 | 8276f25 | 2022-01-07 17:12:31 -0600 | [diff] [blame] | 16 | #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) |
| 17 | #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) |
| johpow01 | ac55c01 | 2022-02-15 22:55:22 -0600 | [diff] [blame] | 18 | #define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) |
| 19 | #define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) |
| Akram Ahmad | 60accba | 2022-07-22 16:20:44 +0100 | [diff] [blame] | 20 | #define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) |
| 21 | #define CORTEX_A510_CPUECTLR_EL1_ATOM U(38) |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 22 | |
| 23 | /******************************************************************************* |
| 24 | * CPU Power Control register specific definitions |
| 25 | ******************************************************************************/ |
| 26 | #define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 27 | #define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 28 | |
| johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame] | 29 | /******************************************************************************* |
| 30 | * Complex auxiliary control register specific definitions |
| 31 | ******************************************************************************/ |
| 32 | #define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 |
| 33 | |
| johpow01 | 49f60dd | 2022-01-06 14:54:49 -0600 | [diff] [blame] | 34 | /******************************************************************************* |
| 35 | * Auxiliary control register specific definitions |
| 36 | ******************************************************************************/ |
| 37 | #define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 |
| Akram Ahmad | a85254e | 2022-07-21 14:01:33 +0100 | [diff] [blame] | 38 | #define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) |
| Akram Ahmad | 89034d6 | 2022-09-21 13:59:56 +0100 | [diff] [blame] | 39 | #define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) |
| johpow01 | 49f60dd | 2022-01-06 14:54:49 -0600 | [diff] [blame] | 40 | |
| Akram Ahmad | 60accba | 2022-07-22 16:20:44 +0100 | [diff] [blame] | 41 | #endif /* CORTEX_A510_H */ |