| commit | a85254ed37e318b885d8742c0aa8541642ce7daf | [log] [tgz] |
|---|---|---|
| author | Akram Ahmad <Akram.Ahmad@arm.com> | Thu Jul 21 14:01:33 2022 +0100 |
| committer | Akram Ahmad <Akram.Ahmad@arm.com> | Tue Aug 30 20:38:27 2022 +0100 |
| tree | 980ca9390d503c5644be66f0348469b57cf83ee8 | |
| parent | b456f74fded470dd8918e7cf3a39f4c3c245fc32 [diff] [blame] |
fix(errata): workaround for Cortex-A510 erratum 2347730 Cortex-A510 erratum 2347730 is a Cat B erratum that affects revisions r0p0, r0p1, r0p2, r0p3, r1p0 and r1p1. It is fixed in r1p2. The workaround is to set CPUACTLR_EL1[17] to 1, which will disable specific microarchitectural clock gating behaviour. SDEN can be found here: https://developer.arm.com/documentation/SDEN1873351/latest https://developer.arm.com/documentation/SDEN1873361/latest Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com> Change-Id: I115386284c2d91bd61515142f971e2e72de43e68
diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h index 83bafda..af38734 100644 --- a/include/lib/cpus/aarch64/cortex_a510.h +++ b/include/lib/cpus/aarch64/cortex_a510.h
@@ -35,5 +35,6 @@ * Auxiliary control register specific definitions ******************************************************************************/ #define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 +#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) #endif /* CORTEX_A510_H */ \ No newline at end of file