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Anson Huangf753d462019-01-15 10:34:04 +08001/*
Jacky Baid746daa12019-11-25 13:19:37 +08002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Anson Huangf753d462019-01-15 10:34:04 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __IMX_SIP_SVC_H__
8#define __IMX_SIP_SVC_H__
9
10/* SMC function IDs for SiP Service queries */
Jacky Bai31f02322019-12-11 16:26:59 +080011#define IMX_SIP_GPC 0xC2000000
12
Anson Huang922c45f2019-01-15 10:56:36 +080013#define IMX_SIP_CPUFREQ 0xC2000001
14#define IMX_SIP_SET_CPUFREQ 0x00
15
Anson Huangf753d462019-01-15 10:34:04 +080016#define IMX_SIP_SRTC 0xC2000002
17#define IMX_SIP_SRTC_SET_TIME 0x00
18
Anson Huang971392d2019-01-18 10:43:59 +080019#define IMX_SIP_BUILDINFO 0xC2000003
20#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00
21
Jacky Baid746daa12019-11-25 13:19:37 +080022#define IMX_SIP_DDR_DVFS 0xc2000004
23
Igor Opaniukf2de6812021-03-10 13:42:55 +020024#define IMX_SIP_SRC 0xC2000005
25#define IMX_SIP_SRC_SET_SECONDARY_BOOT 0x10
26#define IMX_SIP_SRC_IS_SECONDARY_BOOT 0x11
27
Leonard Crestez55119082019-05-10 13:07:41 +030028#define IMX_SIP_GET_SOC_INFO 0xC2000006
29
Anson Huange1d418c2019-01-18 10:01:50 +080030#define IMX_SIP_WAKEUP_SRC 0xC2000009
31#define IMX_SIP_WAKEUP_SRC_SCU 0x1
32#define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2
33
Anson Huang6e47de52019-01-18 10:27:48 +080034#define IMX_SIP_OTP_READ 0xC200000A
35#define IMX_SIP_OTP_WRITE 0xC200000B
36
Anson Huange708bfb2019-01-18 10:35:54 +080037#define IMX_SIP_MISC_SET_TEMP 0xC200000C
38
Peng Fandd860d12020-07-10 14:18:01 +080039#define IMX_SIP_AARCH32 0xC20000FD
40
41int imx_kernel_entry_handler(uint32_t smc_fid, u_register_t x1,
42 u_register_t x2, u_register_t x3,
43 u_register_t x4);
Leonard Crestez55119082019-05-10 13:07:41 +030044#if defined(PLAT_imx8mq)
45int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1,
46 u_register_t x2, u_register_t x3);
47#endif
Jacky Baid746daa12019-11-25 13:19:37 +080048#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
49int dram_dvfs_handler(uint32_t smc_fid, void *handle,
50 u_register_t x1, u_register_t x2, u_register_t x3);
Jacky Bai31f02322019-12-11 16:26:59 +080051
52int imx_gpc_handler(uint32_t smc_fid, u_register_t x1,
53 u_register_t x2, u_register_t x3);
Jacky Baid746daa12019-11-25 13:19:37 +080054#endif
Leonard Crestez55119082019-05-10 13:07:41 +030055
Igor Opaniukf2de6812021-03-10 13:42:55 +020056#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
57int imx_src_handler(uint32_t smc_fid, u_register_t x1,
58 u_register_t x2, u_register_t x3, void *handle);
59#endif
60
Leonard Crestezd62c1612019-05-20 11:28:50 +030061#if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
Anson Huang922c45f2019-01-15 10:56:36 +080062int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1,
63 u_register_t x2, u_register_t x3);
Anson Huangf753d462019-01-15 10:34:04 +080064int imx_srtc_handler(uint32_t smc_fid, void *handle, u_register_t x1,
65 u_register_t x2, u_register_t x3, u_register_t x4);
Anson Huange1d418c2019-01-18 10:01:50 +080066int imx_wakeup_src_handler(uint32_t smc_fid, u_register_t x1,
67 u_register_t x2, u_register_t x3);
Anson Huang6e47de52019-01-18 10:27:48 +080068int imx_otp_handler(uint32_t smc_fid, void *handle,
69 u_register_t x1, u_register_t x2);
Anson Huange708bfb2019-01-18 10:35:54 +080070int imx_misc_set_temp_handler(uint32_t smc_fid, u_register_t x1,
71 u_register_t x2, u_register_t x3,
72 u_register_t x4);
Leonard Crestez402bd522019-05-08 22:29:21 +030073#endif
Anson Huang971392d2019-01-18 10:43:59 +080074uint64_t imx_buildinfo_handler(uint32_t smc_fid, u_register_t x1,
75 u_register_t x2, u_register_t x3,
76 u_register_t x4);
Anson Huangf753d462019-01-15 10:34:04 +080077
78#endif /* __IMX_SIP_SVC_H__ */