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Anson Huangf753d462019-01-15 10:34:04 +08001/*
Jacky Baid746daa2019-11-25 13:19:37 +08002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Anson Huangf753d462019-01-15 10:34:04 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __IMX_SIP_SVC_H__
8#define __IMX_SIP_SVC_H__
9
10/* SMC function IDs for SiP Service queries */
Anson Huang922c45f2019-01-15 10:56:36 +080011#define IMX_SIP_CPUFREQ 0xC2000001
12#define IMX_SIP_SET_CPUFREQ 0x00
13
Anson Huangf753d462019-01-15 10:34:04 +080014#define IMX_SIP_SRTC 0xC2000002
15#define IMX_SIP_SRTC_SET_TIME 0x00
16
Anson Huang971392d2019-01-18 10:43:59 +080017#define IMX_SIP_BUILDINFO 0xC2000003
18#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00
19
Jacky Baid746daa2019-11-25 13:19:37 +080020#define IMX_SIP_DDR_DVFS 0xc2000004
21
Igor Opaniukf2de6812021-03-10 13:42:55 +020022#define IMX_SIP_SRC 0xC2000005
23#define IMX_SIP_SRC_SET_SECONDARY_BOOT 0x10
24#define IMX_SIP_SRC_IS_SECONDARY_BOOT 0x11
25
Leonard Crestez55119082019-05-10 13:07:41 +030026#define IMX_SIP_GET_SOC_INFO 0xC2000006
27
Anson Huange1d418c2019-01-18 10:01:50 +080028#define IMX_SIP_WAKEUP_SRC 0xC2000009
29#define IMX_SIP_WAKEUP_SRC_SCU 0x1
30#define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2
31
Anson Huang6e47de52019-01-18 10:27:48 +080032#define IMX_SIP_OTP_READ 0xC200000A
33#define IMX_SIP_OTP_WRITE 0xC200000B
34
Anson Huange708bfb2019-01-18 10:35:54 +080035#define IMX_SIP_MISC_SET_TEMP 0xC200000C
36
Peng Fandd860d12020-07-10 14:18:01 +080037#define IMX_SIP_AARCH32 0xC20000FD
38
39int imx_kernel_entry_handler(uint32_t smc_fid, u_register_t x1,
40 u_register_t x2, u_register_t x3,
41 u_register_t x4);
Leonard Crestez55119082019-05-10 13:07:41 +030042#if defined(PLAT_imx8mq)
43int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1,
44 u_register_t x2, u_register_t x3);
45#endif
Jacky Baid746daa2019-11-25 13:19:37 +080046#if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
47int dram_dvfs_handler(uint32_t smc_fid, void *handle,
48 u_register_t x1, u_register_t x2, u_register_t x3);
49#endif
Leonard Crestez55119082019-05-10 13:07:41 +030050
Igor Opaniukf2de6812021-03-10 13:42:55 +020051#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
52int imx_src_handler(uint32_t smc_fid, u_register_t x1,
53 u_register_t x2, u_register_t x3, void *handle);
54#endif
55
Leonard Crestezd62c1612019-05-20 11:28:50 +030056#if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
Anson Huang922c45f2019-01-15 10:56:36 +080057int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1,
58 u_register_t x2, u_register_t x3);
Anson Huangf753d462019-01-15 10:34:04 +080059int imx_srtc_handler(uint32_t smc_fid, void *handle, u_register_t x1,
60 u_register_t x2, u_register_t x3, u_register_t x4);
Anson Huange1d418c2019-01-18 10:01:50 +080061int imx_wakeup_src_handler(uint32_t smc_fid, u_register_t x1,
62 u_register_t x2, u_register_t x3);
Anson Huang6e47de52019-01-18 10:27:48 +080063int imx_otp_handler(uint32_t smc_fid, void *handle,
64 u_register_t x1, u_register_t x2);
Anson Huange708bfb2019-01-18 10:35:54 +080065int imx_misc_set_temp_handler(uint32_t smc_fid, u_register_t x1,
66 u_register_t x2, u_register_t x3,
67 u_register_t x4);
Leonard Crestez402bd522019-05-08 22:29:21 +030068#endif
Anson Huang971392d2019-01-18 10:43:59 +080069uint64_t imx_buildinfo_handler(uint32_t smc_fid, u_register_t x1,
70 u_register_t x2, u_register_t x3,
71 u_register_t x4);
Anson Huangf753d462019-01-15 10:34:04 +080072
73#endif /* __IMX_SIP_SVC_H__ */