blob: c259d23ca6585672c83f639f05b0e57f31362041 [file] [log] [blame]
Anson Huangf753d462019-01-15 10:34:04 +08001/*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __IMX_SIP_SVC_H__
8#define __IMX_SIP_SVC_H__
9
10/* SMC function IDs for SiP Service queries */
Anson Huang922c45f2019-01-15 10:56:36 +080011#define IMX_SIP_CPUFREQ 0xC2000001
12#define IMX_SIP_SET_CPUFREQ 0x00
13
Anson Huangf753d462019-01-15 10:34:04 +080014#define IMX_SIP_SRTC 0xC2000002
15#define IMX_SIP_SRTC_SET_TIME 0x00
16
Anson Huange1d418c2019-01-18 10:01:50 +080017#define IMX_SIP_WAKEUP_SRC 0xC2000009
18#define IMX_SIP_WAKEUP_SRC_SCU 0x1
19#define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2
20
Anson Huang6e47de52019-01-18 10:27:48 +080021#define IMX_SIP_OTP_READ 0xC200000A
22#define IMX_SIP_OTP_WRITE 0xC200000B
23
Anson Huange708bfb2019-01-18 10:35:54 +080024#define IMX_SIP_MISC_SET_TEMP 0xC200000C
25
Anson Huangf753d462019-01-15 10:34:04 +080026#if (defined(PLAT_IMX8QM) || defined(PLAT_IMX8QX))
Anson Huang922c45f2019-01-15 10:56:36 +080027int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1,
28 u_register_t x2, u_register_t x3);
Anson Huangf753d462019-01-15 10:34:04 +080029int imx_srtc_handler(uint32_t smc_fid, void *handle, u_register_t x1,
30 u_register_t x2, u_register_t x3, u_register_t x4);
Anson Huange1d418c2019-01-18 10:01:50 +080031int imx_wakeup_src_handler(uint32_t smc_fid, u_register_t x1,
32 u_register_t x2, u_register_t x3);
Anson Huang6e47de52019-01-18 10:27:48 +080033int imx_otp_handler(uint32_t smc_fid, void *handle,
34 u_register_t x1, u_register_t x2);
Anson Huange708bfb2019-01-18 10:35:54 +080035int imx_misc_set_temp_handler(uint32_t smc_fid, u_register_t x1,
36 u_register_t x2, u_register_t x3,
37 u_register_t x4);
Anson Huangf753d462019-01-15 10:34:04 +080038#endif
39
40#endif /* __IMX_SIP_SVC_H__ */