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Varun Wadekar921b9062015-08-25 17:03:14 +05301/*
Varun Wadekar84a775e2019-01-03 10:12:55 -08002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar921b9062015-08-25 17:03:14 +05305 */
6
Varun Wadekarcad7b082015-12-28 18:12:59 -08007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <arch_helpers.h>
10#include <bl31/bl31.h>
11#include <bl31/interrupt_mgmt.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <common/interrupt_props.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080015#include <context.h>
Varun Wadekar4debe052016-05-18 13:39:16 -070016#include <cortex_a57.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080017#include <denver.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018#include <drivers/arm/gic_common.h>
19#include <drivers/arm/gicv2.h>
20#include <drivers/console.h>
21#include <lib/el3_runtime/context_mgmt.h>
22#include <lib/xlat_tables/xlat_tables_v2.h>
23#include <plat/common/platform.h>
24
Varun Wadekar47ddd002016-03-28 16:00:02 -070025#include <mce.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053026#include <tegra_def.h>
Varun Wadekar5887c102016-07-19 11:29:40 -070027#include <tegra_platform.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080028#include <tegra_private.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053029
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080030/*******************************************************************************
Varun Wadekar43dad672017-01-31 14:53:37 -080031 * Tegra186 CPU numbers in cluster #0
32 *******************************************************************************
33 */
Anthony Zhou25d127f2017-03-21 15:58:50 +080034#define TEGRA186_CLUSTER0_CORE2 2U
35#define TEGRA186_CLUSTER0_CORE3 3U
Varun Wadekar43dad672017-01-31 14:53:37 -080036
37/*******************************************************************************
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080038 * The Tegra power domain tree has a single system level power domain i.e. a
39 * single root node. The first entry in the power domain descriptor specifies
40 * the number of power domains at the highest power level.
41 *******************************************************************************
42 */
Anthony Zhou0895a8f2017-09-22 16:52:02 +080043static const uint8_t tegra_power_domain_tree_desc[] = {
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080044 /* No of root nodes */
45 1,
46 /* No of clusters */
47 PLATFORM_CLUSTER_COUNT,
48 /* No of CPU cores - cluster0 */
49 PLATFORM_MAX_CPUS_PER_CLUSTER,
50 /* No of CPU cores - cluster1 */
51 PLATFORM_MAX_CPUS_PER_CLUSTER
52};
53
Varun Wadekare34bc3d2017-04-28 08:43:33 -070054/*******************************************************************************
55 * This function returns the Tegra default topology tree information.
56 ******************************************************************************/
Anthony Zhou25d127f2017-03-21 15:58:50 +080057const uint8_t *plat_get_power_domain_tree_desc(void)
Varun Wadekare34bc3d2017-04-28 08:43:33 -070058{
59 return tegra_power_domain_tree_desc;
60}
61
Varun Wadekar921b9062015-08-25 17:03:14 +053062/*
63 * Table of regions to map using the MMU.
64 */
65static const mmap_region_t tegra_mmap[] = {
Anthony Zhou25d127f2017-03-21 15:58:50 +080066 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053067 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080068 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
Varun Wadekara0f26972016-03-11 17:18:51 -080069 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080070 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053071 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080072 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053073 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080074 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
Varun Wadekar9db0ad12016-07-12 10:04:28 -070075 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080076 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
Varun Wadekar9db0ad12016-07-12 10:04:28 -070077 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080078 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
Varun Wadekar921b9062015-08-25 17:03:14 +053079 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080080 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
Varun Wadekar4debe052016-05-18 13:39:16 -070081 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080082 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053083 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080084 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -080085 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080086 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -080087 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080088 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -080089 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080090 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
Varun Wadekare60f1bf2016-02-17 10:10:50 -080091 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080092 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053093 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar922550a2018-01-23 14:38:51 -080094 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */
95 MT_DEVICE | MT_RO | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080096 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -080097 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080098 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053099 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +0800100 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000U, /* 128KB - ARM/Denver */
Varun Wadekard64db962016-09-23 14:28:16 -0700101 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +0800102 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +0530103 MT_DEVICE | MT_RW | MT_SECURE),
104 {0}
105};
106
107/*******************************************************************************
108 * Set up the pagetables as per the platform memory map & initialize the MMU
109 ******************************************************************************/
110const mmap_region_t *plat_get_mmio_map(void)
111{
112 /* MMIO space */
113 return tegra_mmap;
114}
115
116/*******************************************************************************
117 * Handler to get the System Counter Frequency
118 ******************************************************************************/
Anthony Zhou25d127f2017-03-21 15:58:50 +0800119uint32_t plat_get_syscnt_freq2(void)
Varun Wadekar921b9062015-08-25 17:03:14 +0530120{
Varun Wadekar20c94292016-01-04 10:57:45 -0800121 return 31250000;
Varun Wadekar921b9062015-08-25 17:03:14 +0530122}
123
124/*******************************************************************************
125 * Maximum supported UART controllers
126 ******************************************************************************/
127#define TEGRA186_MAX_UART_PORTS 7
128
129/*******************************************************************************
130 * This variable holds the UART port base addresses
131 ******************************************************************************/
132static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
133 0, /* undefined - treated as an error case */
134 TEGRA_UARTA_BASE,
135 TEGRA_UARTB_BASE,
136 TEGRA_UARTC_BASE,
137 TEGRA_UARTD_BASE,
138 TEGRA_UARTE_BASE,
139 TEGRA_UARTF_BASE,
140 TEGRA_UARTG_BASE,
141};
142
143/*******************************************************************************
144 * Retrieve the UART controller base to be used as the console
145 ******************************************************************************/
Anthony Zhou25d127f2017-03-21 15:58:50 +0800146uint32_t plat_get_console_from_id(int32_t id)
Varun Wadekar921b9062015-08-25 17:03:14 +0530147{
Anthony Zhou25d127f2017-03-21 15:58:50 +0800148 uint32_t ret;
Varun Wadekar921b9062015-08-25 17:03:14 +0530149
Anthony Zhou25d127f2017-03-21 15:58:50 +0800150 if (id > TEGRA186_MAX_UART_PORTS) {
151 ret = 0;
152 } else {
153 ret = tegra186_uart_addresses[id];
154 }
155
156 return ret;
Varun Wadekar921b9062015-08-25 17:03:14 +0530157}
Varun Wadekarcad7b082015-12-28 18:12:59 -0800158
Varun Wadekar4debe052016-05-18 13:39:16 -0700159/*******************************************************************************
160 * Handler for early platform setup
161 ******************************************************************************/
162void plat_early_platform_setup(void)
163{
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800164 uint64_t impl, val;
165 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
Varun Wadekar4debe052016-05-18 13:39:16 -0700166
167 /* sanity check MCE firmware compatibility */
168 mce_verify_firmware_version();
169
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800170 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
171
Varun Wadekar4debe052016-05-18 13:39:16 -0700172 /*
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800173 * Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186
174 * A02p and beyond).
Varun Wadekar4debe052016-05-18 13:39:16 -0700175 */
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800176 if ((plat_params->l2_ecc_parity_prot_dis != 1) &&
177 (impl != (uint64_t)DENVER_IMPL)) {
Varun Wadekar4debe052016-05-18 13:39:16 -0700178
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800179 val = read_l2ctlr_el1();
Anthony Zhou25d127f2017-03-21 15:58:50 +0800180 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800181 write_l2ctlr_el1(val);
Varun Wadekar4debe052016-05-18 13:39:16 -0700182 }
183}
184
Varun Wadekarcad7b082015-12-28 18:12:59 -0800185/* Secure IRQs for Tegra186 */
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700186static const interrupt_prop_t tegra186_interrupt_props[] = {
187 INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
188 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
189 INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
190 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
Varun Wadekarcad7b082015-12-28 18:12:59 -0800191};
192
193/*******************************************************************************
194 * Initialize the GIC and SGIs
195 ******************************************************************************/
196void plat_gic_setup(void)
197{
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700198 tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props));
Varun Wadekar84a775e2019-01-03 10:12:55 -0800199 tegra_gic_init();
Varun Wadekarcad7b082015-12-28 18:12:59 -0800200
201 /*
202 * Initialize the FIQ handler only if the platform supports any
203 * FIQ interrupt sources.
204 */
Varun Wadekar84a775e2019-01-03 10:12:55 -0800205 tegra_fiq_handler_setup();
Varun Wadekarcad7b082015-12-28 18:12:59 -0800206}
Varun Wadekar94701ff2016-05-23 11:47:34 -0700207
208/*******************************************************************************
209 * Return pointer to the BL31 params from previous bootloader
210 ******************************************************************************/
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100211struct tegra_bl31_params *plat_get_bl31_params(void)
Varun Wadekar94701ff2016-05-23 11:47:34 -0700212{
213 uint32_t val;
214
Steven Kao186485e2017-10-23 18:22:09 +0800215 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
Varun Wadekar94701ff2016-05-23 11:47:34 -0700216
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100217 return (struct tegra_bl31_params *)(uintptr_t)val;
Varun Wadekar94701ff2016-05-23 11:47:34 -0700218}
219
220/*******************************************************************************
221 * Return pointer to the BL31 platform params from previous bootloader
222 ******************************************************************************/
223plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
224{
225 uint32_t val;
226
Steven Kao186485e2017-10-23 18:22:09 +0800227 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
Varun Wadekar94701ff2016-05-23 11:47:34 -0700228
229 return (plat_params_from_bl2_t *)(uintptr_t)val;
230}
Varun Wadekar43dad672017-01-31 14:53:37 -0800231
232/*******************************************************************************
233 * This function implements a part of the critical interface between the psci
234 * generic layer and the platform that allows the former to query the platform
235 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
236 * in case the MPIDR is invalid.
237 ******************************************************************************/
Anthony Zhou25d127f2017-03-21 15:58:50 +0800238int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
Varun Wadekar43dad672017-01-31 14:53:37 -0800239{
Anthony Zhou25d127f2017-03-21 15:58:50 +0800240 u_register_t cluster_id, cpu_id, pos;
241 int32_t ret;
Varun Wadekar43dad672017-01-31 14:53:37 -0800242
Anthony Zhou25d127f2017-03-21 15:58:50 +0800243 cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
244 cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
Varun Wadekar43dad672017-01-31 14:53:37 -0800245
246 /*
247 * Validate cluster_id by checking whether it represents
248 * one of the two clusters present on the platform.
Varun Wadekar43dad672017-01-31 14:53:37 -0800249 * Validate cpu_id by checking whether it represents a CPU in
250 * one of the two clusters present on the platform.
251 */
Anthony Zhou25d127f2017-03-21 15:58:50 +0800252 if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) ||
253 (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) {
254 ret = PSCI_E_NOT_PRESENT;
255 } else {
256 /* calculate the core position */
257 pos = cpu_id + (cluster_id << 2U);
Varun Wadekar43dad672017-01-31 14:53:37 -0800258
Anthony Zhou25d127f2017-03-21 15:58:50 +0800259 /* check for non-existent CPUs */
260 if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) {
261 ret = PSCI_E_NOT_PRESENT;
262 } else {
263 ret = (int32_t)pos;
264 }
265 }
Varun Wadekar43dad672017-01-31 14:53:37 -0800266
Anthony Zhou25d127f2017-03-21 15:58:50 +0800267 return ret;
Varun Wadekar43dad672017-01-31 14:53:37 -0800268}