Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Manish V Badarkhe | 56808e4 | 2021-05-23 13:16:46 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Alexei Fedorov | 25d7c88 | 2020-03-20 18:38:55 +0000 | [diff] [blame] | 7 | #include <assert.h> |
Manish V Badarkhe | 56808e4 | 2021-05-23 13:16:46 +0100 | [diff] [blame] | 8 | #include <errno.h> |
Alexei Fedorov | 25d7c88 | 2020-03-20 18:38:55 +0000 | [diff] [blame] | 9 | |
| 10 | #include <bl1/bl1.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <common/tbbr/tbbr_img_def.h> |
Alexei Fedorov | 896799a | 2019-05-09 12:14:40 +0100 | [diff] [blame] | 12 | #include <drivers/arm/smmu_v3.h> |
Aditya Angadi | 20b4841 | 2019-04-16 11:29:14 +0530 | [diff] [blame] | 13 | #include <drivers/arm/sp805.h> |
Manish V Badarkhe | 56808e4 | 2021-05-23 13:16:46 +0100 | [diff] [blame] | 14 | #include <lib/mmio.h> |
Alexei Fedorov | 896799a | 2019-05-09 12:14:40 +0100 | [diff] [blame] | 15 | #include <plat/arm/common/arm_config.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 16 | #include <plat/arm/common/plat_arm.h> |
Aditya Angadi | 20b4841 | 2019-04-16 11:29:14 +0530 | [diff] [blame] | 17 | #include <plat/arm/common/arm_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 18 | #include <plat/common/platform.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 19 | #include "fvp_private.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 20 | |
| 21 | /******************************************************************************* |
| 22 | * Perform any BL1 specific platform actions. |
| 23 | ******************************************************************************/ |
| 24 | void bl1_early_platform_setup(void) |
| 25 | { |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 26 | arm_bl1_early_platform_setup(); |
Sandrine Bailleux | e3060e2 | 2014-06-13 14:48:18 +0100 | [diff] [blame] | 27 | |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 28 | /* Initialize the platform config for future decision making */ |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 29 | fvp_config_setup(); |
James Morrissey | 9d72b4e | 2014-02-10 17:04:32 +0000 | [diff] [blame] | 30 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 31 | /* |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 32 | * Initialize Interconnect for this cluster during cold boot. |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 33 | * No need for locks as no other CPU is active. |
| 34 | */ |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 35 | fvp_interconnect_init(); |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 36 | /* |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 37 | * Enable coherency in Interconnect for the primary CPU's cluster. |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 38 | */ |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 39 | fvp_interconnect_enable(); |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 40 | } |
Aditya Angadi | 20b4841 | 2019-04-16 11:29:14 +0530 | [diff] [blame] | 41 | |
| 42 | void plat_arm_secure_wdt_start(void) |
| 43 | { |
| 44 | sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); |
| 45 | } |
| 46 | |
| 47 | void plat_arm_secure_wdt_stop(void) |
| 48 | { |
| 49 | sp805_stop(ARM_SP805_TWDG_BASE); |
| 50 | } |
Alexei Fedorov | 896799a | 2019-05-09 12:14:40 +0100 | [diff] [blame] | 51 | |
| 52 | void bl1_platform_setup(void) |
| 53 | { |
| 54 | arm_bl1_platform_setup(); |
| 55 | |
Alexei Fedorov | 7131d83 | 2019-08-16 14:15:59 +0100 | [diff] [blame] | 56 | /* Initialize System level generic or SP804 timer */ |
| 57 | fvp_timer_init(); |
| 58 | |
Alexei Fedorov | 896799a | 2019-05-09 12:14:40 +0100 | [diff] [blame] | 59 | /* On FVP RevC, initialize SMMUv3 */ |
| 60 | if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) |
| 61 | smmuv3_security_init(PLAT_FVP_SMMUV3_BASE); |
| 62 | } |
Ambroise Vincent | fa42c9e | 2019-07-04 14:58:45 +0100 | [diff] [blame] | 63 | |
| 64 | __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved) |
| 65 | { |
Manish V Badarkhe | 56808e4 | 2021-05-23 13:16:46 +0100 | [diff] [blame] | 66 | uint32_t nv_flags = mmio_read_32(V2M_SYS_NVFLAGS_ADDR); |
| 67 | |
| 68 | /* Clear the NV flags register. */ |
| 69 | mmio_write_32((V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR), |
| 70 | nv_flags); |
| 71 | |
Ambroise Vincent | fa42c9e | 2019-07-04 14:58:45 +0100 | [diff] [blame] | 72 | /* Setup the watchdog to reset the system as soon as possible */ |
| 73 | sp805_refresh(ARM_SP805_TWDG_BASE, 1U); |
| 74 | |
Jimmy Brisson | 471550a | 2020-08-06 10:50:15 -0500 | [diff] [blame] | 75 | while (true) |
Ambroise Vincent | fa42c9e | 2019-07-04 14:58:45 +0100 | [diff] [blame] | 76 | wfi(); |
| 77 | } |
Alexei Fedorov | 25d7c88 | 2020-03-20 18:38:55 +0000 | [diff] [blame] | 78 | |
Manish V Badarkhe | 56808e4 | 2021-05-23 13:16:46 +0100 | [diff] [blame] | 79 | /******************************************************************************* |
| 80 | * The following function checks if Firmware update is needed by checking error |
| 81 | * reported in NV flag. |
| 82 | ******************************************************************************/ |
| 83 | bool plat_arm_bl1_fwu_needed(void) |
| 84 | { |
| 85 | int32_t nv_flags = (int32_t)mmio_read_32(V2M_SYS_NVFLAGS_ADDR); |
| 86 | |
| 87 | /* if image load/authentication failed */ |
| 88 | return ((nv_flags == -EAUTH) || (nv_flags == -ENOENT)); |
| 89 | } |