Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | cbccdbf | 2019-01-21 11:53:29 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <drivers/arm/tzc400.h> |
| 11 | #include <lib/utils_def.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 12 | #include <plat/arm/board/common/v2m_def.h> |
| 13 | #include <plat/arm/common/arm_def.h> |
| 14 | #include <plat/arm/common/arm_spm_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <plat/common/common_def.h> |
| 16 | |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 17 | #include "../fvp_def.h" |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 18 | |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 19 | /* Required platform porting definitions */ |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 20 | #define PLATFORM_CORE_COUNT \ |
| 21 | (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) |
| 22 | |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 23 | #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 24 | PLATFORM_CORE_COUNT) + 1 |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 25 | |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 26 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 27 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 28 | /* |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 29 | * Other platform porting definitions are provided by included headers |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 30 | */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 31 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 32 | /* |
| 33 | * Required ARM standard platform porting definitions |
| 34 | */ |
Soby Mathew | 47e43f2 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 35 | #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 36 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 37 | #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 38 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 39 | #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) |
| 40 | #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 41 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 42 | #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) |
| 43 | #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 44 | |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 45 | /* virtual address used by dynamic mem_protect for chunk_base */ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 46 | #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 47 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 48 | /* No SCP in FVP */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 49 | #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 50 | |
Sami Mujawar | a43ae7c | 2019-05-09 13:35:02 +0100 | [diff] [blame] | 51 | #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 52 | #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) |
Juan Castillo | d227d8b | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 53 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 54 | /* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 55 | * Load address of BL33 for this platform port |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 56 | */ |
Sandrine Bailleux | afa91db | 2019-01-31 15:01:32 +0100 | [diff] [blame] | 57 | #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 58 | |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 59 | /* |
| 60 | * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the |
| 61 | * plat_arm_mmap array defined for each BL stage. |
| 62 | */ |
| 63 | #if defined(IMAGE_BL31) |
| 64 | # if ENABLE_SPM |
| 65 | # define PLAT_ARM_MMAP_ENTRIES 9 |
Antonio Nino Diaz | 840627f | 2018-11-27 08:36:02 +0000 | [diff] [blame] | 66 | # define MAX_XLAT_TABLES 9 |
| 67 | # define PLAT_SP_IMAGE_MMAP_REGIONS 30 |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 68 | # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 |
| 69 | # else |
| 70 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 71 | # define MAX_XLAT_TABLES 5 |
| 72 | # endif |
| 73 | #elif defined(IMAGE_BL32) |
| 74 | # define PLAT_ARM_MMAP_ENTRIES 8 |
| 75 | # define MAX_XLAT_TABLES 5 |
| 76 | #elif !USE_ROMLIB |
| 77 | # define PLAT_ARM_MMAP_ENTRIES 11 |
| 78 | # define MAX_XLAT_TABLES 5 |
| 79 | #else |
| 80 | # define PLAT_ARM_MMAP_ENTRIES 12 |
| 81 | # define MAX_XLAT_TABLES 6 |
| 82 | #endif |
| 83 | |
| 84 | /* |
| 85 | * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size |
| 86 | * plus a little space for growth. |
| 87 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 88 | #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 89 | |
| 90 | /* |
| 91 | * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page |
| 92 | */ |
| 93 | |
| 94 | #if USE_ROMLIB |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 95 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) |
| 96 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 97 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 98 | #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) |
| 99 | #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 100 | #endif |
| 101 | |
| 102 | /* |
| 103 | * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a |
| 104 | * little space for growth. |
| 105 | */ |
| 106 | #if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 107 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 108 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 109 | # define PLAT_ARM_MAX_BL2_SIZE UL(0x11000) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 110 | #endif |
| 111 | |
| 112 | /* |
| 113 | * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is |
| 114 | * calculated using the current BL31 PROGBITS debug size plus the sizes of |
| 115 | * BL2 and BL1-RW |
| 116 | */ |
Antonio Nino Diaz | cbccdbf | 2019-01-21 11:53:29 +0000 | [diff] [blame] | 117 | #if ENABLE_SPM && !SPM_MM |
Antonio Nino Diaz | 675d155 | 2018-10-30 11:36:47 +0000 | [diff] [blame] | 118 | #define PLAT_ARM_MAX_BL31_SIZE UL(0x60000) |
| 119 | #else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 120 | #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) |
Antonio Nino Diaz | 675d155 | 2018-10-30 11:36:47 +0000 | [diff] [blame] | 121 | #endif |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 122 | |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 123 | #ifndef __aarch64__ |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 124 | /* |
| 125 | * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is |
| 126 | * calculated using the current SP_MIN PROGBITS debug size plus the sizes of |
| 127 | * BL2 and BL1-RW |
| 128 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 129 | # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) |
Antonio Nino Diaz | 9202926 | 2018-09-28 16:39:26 +0100 | [diff] [blame] | 130 | #endif |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 131 | |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 132 | /* |
| 133 | * Size of cacheable stacks |
| 134 | */ |
| 135 | #if defined(IMAGE_BL1) |
| 136 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 137 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 138 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 139 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 140 | # endif |
| 141 | #elif defined(IMAGE_BL2) |
| 142 | # if TRUSTED_BOARD_BOOT |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 143 | # define PLATFORM_STACK_SIZE UL(0x1000) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 144 | # else |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 145 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 146 | # endif |
| 147 | #elif defined(IMAGE_BL2U) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 148 | # define PLATFORM_STACK_SIZE UL(0x400) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 149 | #elif defined(IMAGE_BL31) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 150 | # define PLATFORM_STACK_SIZE UL(0x800) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 151 | #elif defined(IMAGE_BL32) |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 152 | # define PLATFORM_STACK_SIZE UL(0x440) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 153 | #endif |
| 154 | |
| 155 | #define MAX_IO_DEVICES 3 |
| 156 | #define MAX_IO_HANDLES 4 |
| 157 | |
| 158 | /* Reserve the last block of flash for PSCI MEM PROTECT flag */ |
| 159 | #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE |
| 160 | #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 161 | |
| 162 | #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE |
| 163 | #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 164 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 165 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 166 | * PL011 related constants |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 167 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 168 | #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE |
| 169 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 170 | |
Usama Arif | 81eb5ce | 2019-02-11 16:35:42 +0000 | [diff] [blame] | 171 | #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE |
| 172 | #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ |
Soby Mathew | 2fd66be | 2015-12-09 11:38:43 +0000 | [diff] [blame] | 173 | |
Usama Arif | 81eb5ce | 2019-02-11 16:35:42 +0000 | [diff] [blame] | 174 | #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE |
| 175 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 176 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 177 | #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE |
| 178 | #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 179 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 180 | #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 181 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 182 | /* CCI related constants */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 183 | #define PLAT_FVP_CCI400_BASE UL(0x2c090000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 184 | #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 |
| 185 | #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 |
| 186 | |
| 187 | /* CCI-500/CCI-550 on Base platform */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 188 | #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) |
Jeenu Viswambharan | 9e78b92 | 2017-07-18 15:42:50 +0100 | [diff] [blame] | 189 | #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 |
| 190 | #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 |
Juan Castillo | e33ee5f | 2014-12-19 09:51:00 +0000 | [diff] [blame] | 191 | |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 192 | /* CCN related constants. Only CCN 502 is currently supported */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 193 | #define PLAT_ARM_CCN_BASE UL(0x2e000000) |
Soby Mathew | 7356b1e | 2016-03-24 10:12:42 +0000 | [diff] [blame] | 194 | #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 |
| 195 | |
Vikram Kanigiri | a2cee03 | 2015-07-31 16:35:05 +0100 | [diff] [blame] | 196 | /* System timer related constants */ |
Antonio Nino Diaz | 6971f00 | 2018-11-06 13:14:21 +0000 | [diff] [blame] | 197 | #define PLAT_ARM_NSTIMER_FRAME_ID U(1) |
Vikram Kanigiri | a2cee03 | 2015-07-31 16:35:05 +0100 | [diff] [blame] | 198 | |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 199 | /* Mailbox base address */ |
| 200 | #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE |
| 201 | |
| 202 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 203 | /* TrustZone controller related constants |
| 204 | * |
| 205 | * Currently only filters 0 and 2 are connected on Base FVP. |
| 206 | * Filter 0 : CPU clusters (no access to DRAM by default) |
| 207 | * Filter 1 : not connected |
| 208 | * Filter 2 : LCDs (access to VRAM allowed by default) |
| 209 | * Filter 3 : not connected |
| 210 | * Programming unconnected filters will have no effect at the |
| 211 | * moment. These filter could, however, be connected in future. |
| 212 | * So care should be taken not to configure the unused filters. |
| 213 | * |
| 214 | * Allow only non-secure access to all DRAM to supported devices. |
| 215 | * Give access to the CPUs and Virtio. Some devices |
| 216 | * would normally use the default ID so allow that too. |
| 217 | */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 218 | #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) |
Soby Mathew | 9c708b5 | 2016-02-26 14:23:19 +0000 | [diff] [blame] | 219 | #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 220 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 221 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 222 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ |
| 223 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ |
| 224 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ |
| 225 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ |
| 226 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 227 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 228 | /* |
| 229 | * GIC related constants to cater for both GICv2 and GICv3 instances of an |
| 230 | * FVP. They could be overriden at runtime in case the FVP implements the legacy |
| 231 | * VE memory map. |
| 232 | */ |
| 233 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 234 | #define PLAT_ARM_GICR_BASE BASE_GICR_BASE |
| 235 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 236 | |
| 237 | /* |
| 238 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 239 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 240 | * as Group 0 interrupts. |
| 241 | */ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 242 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 243 | ARM_G1S_IRQ_PROPS(grp), \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 244 | INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 245 | GIC_INTR_CFG_LEVEL), \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 246 | INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 247 | GIC_INTR_CFG_LEVEL) |
| 248 | |
| 249 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 250 | |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 251 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS |
| 252 | #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS |
| 253 | |
Ard Biesheuvel | 8b034fc | 2018-12-29 19:43:21 +0100 | [diff] [blame] | 254 | #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ |
| 255 | PLAT_SP_IMAGE_NS_BUF_SIZE) |
Sughosh Ganu | 5f21294 | 2018-05-16 15:35:25 +0530 | [diff] [blame] | 256 | |
Sughosh Ganu | d284b57 | 2018-11-14 10:42:46 +0530 | [diff] [blame] | 257 | #define PLAT_SP_PRI PLAT_RAS_PRI |
| 258 | |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 259 | /* |
| 260 | * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes |
| 261 | */ |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 262 | #ifdef __aarch64__ |
Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 263 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 264 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
| 265 | #else |
| 266 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 267 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 268 | #endif |
| 269 | |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 270 | #endif /* PLATFORM_DEF_H */ |