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git01.mediatek.com / filogic / atf / 503bbf3db02ab294ec95827788453fb5bb5cf797 / . / include / plat / arm / common / aarch64 / arm_macros.S
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Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]1/*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000[diff] [blame]2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]5 */
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]6#ifndef ARM_MACROS_S
7#define ARM_MACROS_S
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]8
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]9#include <drivers/arm/gic_common.h>
10#include <drivers/arm/gicv2.h>
11#include <drivers/arm/gicv3.h>
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]12#include <platform_def.h>
13
14.section .rodata.gic_reg_name, "aS"
Soby Mathew12012dd2015-10-26 14:01:53 +0000[diff] [blame]15/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]16gicc_regs:
17 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
Soby Mathew12012dd2015-10-26 14:01:53 +0000[diff] [blame]18
19/* Applicable only to GICv3 with SRE enabled */
20icc_regs:
21 .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
22
23/* Registers common to both GICv2 and GICv3 */
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]24gicd_pend_reg:
Roberto Vargas1a1d19f2018-04-30 17:58:58 +0100[diff] [blame]25 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]26newline:
27 .asciz "\n"
28spacer:
29 .asciz ":\t\t0x"
30
31 /* ---------------------------------------------
32 * The below utility macro prints out relevant GIC
33 * registers whenever an unhandled exception is
Juan Castillo7d199412015-12-14 09:35:25 +0000[diff] [blame]34 * taken in BL31 on ARM standard platforms.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]35 * Expects: GICD base in x16, GICC base in x17
36 * Clobbers: x0 - x10, sp
37 * ---------------------------------------------
38 */
39 .macro arm_print_gic_regs
Soby Mathew12012dd2015-10-26 14:01:53 +0000[diff] [blame]40 /* Check for GICv3 system register access */
41 mrs x7, id_aa64pfr0_el1
42 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
43 cmp x7, #1
44 b.ne print_gicv2
45
46 /* Check for SRE enable */
47 mrs x8, ICC_SRE_EL3
48 tst x8, #ICC_SRE_SRE_BIT
49 b.eq print_gicv2
50
51 /* Load the icc reg list to x6 */
52 adr x6, icc_regs
53 /* Load the icc regs to gp regs used by str_in_crash_buf_print */
54 mrs x8, ICC_HPPIR0_EL1
55 mrs x9, ICC_HPPIR1_EL1
56 mrs x10, ICC_CTLR_EL3
57 /* Store to the crash buf and print to console */
58 bl str_in_crash_buf_print
59 b print_gic_common
60
61print_gicv2:
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]62 /* Load the gicc reg list to x6 */
63 adr x6, gicc_regs
64 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
65 ldr w8, [x17, #GICC_HPPIR]
66 ldr w9, [x17, #GICC_AHPPIR]
67 ldr w10, [x17, #GICC_CTLR]
68 /* Store to the crash buf and print to console */
69 bl str_in_crash_buf_print
70
Soby Mathew12012dd2015-10-26 14:01:53 +0000[diff] [blame]71print_gic_common:
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]72 /* Print the GICD_ISPENDR regs */
73 add x7, x16, #GICD_ISPENDR
74 adr x4, gicd_pend_reg
75 bl asm_print_str
76gicd_ispendr_loop:
77 sub x4, x7, x16
78 cmp x4, #0x280
79 b.eq exit_print_gic_regs
80 bl asm_print_hex
81
82 adr x4, spacer
83 bl asm_print_str
84
85 ldr x4, [x7], #8
86 bl asm_print_hex
87
88 adr x4, newline
89 bl asm_print_str
90 b gicd_ispendr_loop
91exit_print_gic_regs:
92 .endm
93
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]94#endif /* ARM_MACROS_S */