Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | #ifndef __ARM_MACROS_S__ |
| 31 | #define __ARM_MACROS_S__ |
| 32 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 33 | #include <gic_common.h> |
| 34 | #include <gicv2.h> |
| 35 | #include <gicv3.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 36 | #include <platform_def.h> |
| 37 | |
| 38 | .section .rodata.gic_reg_name, "aS" |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 39 | /* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 40 | gicc_regs: |
| 41 | .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 42 | |
| 43 | /* Applicable only to GICv3 with SRE enabled */ |
| 44 | icc_regs: |
| 45 | .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" |
| 46 | |
| 47 | /* Registers common to both GICv2 and GICv3 */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 48 | gicd_pend_reg: |
| 49 | .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ |
| 50 | " Offset:\t\t\tvalue\n" |
| 51 | newline: |
| 52 | .asciz "\n" |
| 53 | spacer: |
| 54 | .asciz ":\t\t0x" |
| 55 | |
| 56 | /* --------------------------------------------- |
| 57 | * The below utility macro prints out relevant GIC |
| 58 | * registers whenever an unhandled exception is |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 59 | * taken in BL31 on ARM standard platforms. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 60 | * Expects: GICD base in x16, GICC base in x17 |
| 61 | * Clobbers: x0 - x10, sp |
| 62 | * --------------------------------------------- |
| 63 | */ |
| 64 | .macro arm_print_gic_regs |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 65 | /* Check for GICv3 system register access */ |
| 66 | mrs x7, id_aa64pfr0_el1 |
| 67 | ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH |
| 68 | cmp x7, #1 |
| 69 | b.ne print_gicv2 |
| 70 | |
| 71 | /* Check for SRE enable */ |
| 72 | mrs x8, ICC_SRE_EL3 |
| 73 | tst x8, #ICC_SRE_SRE_BIT |
| 74 | b.eq print_gicv2 |
| 75 | |
| 76 | /* Load the icc reg list to x6 */ |
| 77 | adr x6, icc_regs |
| 78 | /* Load the icc regs to gp regs used by str_in_crash_buf_print */ |
| 79 | mrs x8, ICC_HPPIR0_EL1 |
| 80 | mrs x9, ICC_HPPIR1_EL1 |
| 81 | mrs x10, ICC_CTLR_EL3 |
| 82 | /* Store to the crash buf and print to console */ |
| 83 | bl str_in_crash_buf_print |
| 84 | b print_gic_common |
| 85 | |
| 86 | print_gicv2: |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 87 | /* Load the gicc reg list to x6 */ |
| 88 | adr x6, gicc_regs |
| 89 | /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ |
| 90 | ldr w8, [x17, #GICC_HPPIR] |
| 91 | ldr w9, [x17, #GICC_AHPPIR] |
| 92 | ldr w10, [x17, #GICC_CTLR] |
| 93 | /* Store to the crash buf and print to console */ |
| 94 | bl str_in_crash_buf_print |
| 95 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 96 | print_gic_common: |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 97 | /* Print the GICD_ISPENDR regs */ |
| 98 | add x7, x16, #GICD_ISPENDR |
| 99 | adr x4, gicd_pend_reg |
| 100 | bl asm_print_str |
| 101 | gicd_ispendr_loop: |
| 102 | sub x4, x7, x16 |
| 103 | cmp x4, #0x280 |
| 104 | b.eq exit_print_gic_regs |
| 105 | bl asm_print_hex |
| 106 | |
| 107 | adr x4, spacer |
| 108 | bl asm_print_str |
| 109 | |
| 110 | ldr x4, [x7], #8 |
| 111 | bl asm_print_hex |
| 112 | |
| 113 | adr x4, newline |
| 114 | bl asm_print_str |
| 115 | b gicd_ispendr_loop |
| 116 | exit_print_gic_regs: |
| 117 | .endm |
| 118 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 119 | #endif /* __ARM_MACROS_S__ */ |