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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Roberto Vargas777dd432018-02-12 12:36:17 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +01007#ifndef PSCI_PRIVATE_H
8#define PSCI_PRIVATE_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Achin Guptaa59caa42013-12-05 14:21:04 +000010#include <arch.h>
Antonio Nino Diazdd0e85c2018-07-17 09:51:33 +010011#include <arch_helpers.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010012#include <bakery_lock.h>
Soby Mathew8595b872015-01-06 15:36:38 +000013#include <bl_common.h>
Soby Mathew981487a2015-07-13 14:10:57 +010014#include <cpu_data.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010015#include <psci.h>
Soby Mathew981487a2015-07-13 14:10:57 +010016#include <spinlock.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010017
Soby Mathew6cdddaf2015-01-07 11:10:22 +000018/*
19 * The PSCI capability which are provided by the generic code but does not
20 * depend on the platform or spd capabilities.
21 */
22#define PSCI_GENERIC_CAP \
23 (define_psci_cap(PSCI_VERSION) | \
24 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \
25 define_psci_cap(PSCI_FEATURES))
26
27/*
28 * The PSCI capabilities mask for 64 bit functions.
29 */
30#define PSCI_CAP_64BIT_MASK \
31 (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \
32 define_psci_cap(PSCI_CPU_ON_AARCH64) | \
33 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \
34 define_psci_cap(PSCI_MIG_AARCH64) | \
Soby Mathew96168382014-12-17 14:47:57 +000035 define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +010036 define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010037 define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \
38 define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \
Roberto Vargasb820ad02017-07-26 09:23:09 +010039 define_psci_cap(PSCI_STAT_COUNT_AARCH64) | \
Roberto Vargas653fb8f2017-10-12 10:57:40 +010040 define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \
41 define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64))
Soby Mathew6cdddaf2015-01-07 11:10:22 +000042
Soby Mathew981487a2015-07-13 14:10:57 +010043/*
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010044 * Helper functions to get/set the fields of PSCI per-cpu data.
Soby Mathew981487a2015-07-13 14:10:57 +010045 */
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010046static inline void psci_set_aff_info_state(aff_info_state_t aff_state)
47{
48 set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state);
49}
Soby Mathew981487a2015-07-13 14:10:57 +010050
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010051static inline aff_info_state_t psci_get_aff_info_state(void)
52{
53 return get_cpu_data(psci_svc_cpu_data.aff_info_state);
54}
55
56static inline aff_info_state_t psci_get_aff_info_state_by_idx(int idx)
57{
58 return get_cpu_data_by_index((unsigned int)idx,
59 psci_svc_cpu_data.aff_info_state);
60}
61
62static inline void psci_set_aff_info_state_by_idx(int idx,
63 aff_info_state_t aff_state)
64{
65 set_cpu_data_by_index((unsigned int)idx,
66 psci_svc_cpu_data.aff_info_state, aff_state);
67}
68
69static inline unsigned int psci_get_suspend_pwrlvl(void)
70{
71 return get_cpu_data(psci_svc_cpu_data.target_pwrlvl);
72}
Soby Mathew981487a2015-07-13 14:10:57 +010073
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010074static inline void psci_set_suspend_pwrlvl(unsigned int target_lvl)
75{
76 set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl);
77}
78
79static inline void psci_set_cpu_local_state(plat_local_state_t state)
80{
81 set_cpu_data(psci_svc_cpu_data.local_state, state);
82}
83
84static inline plat_local_state_t psci_get_cpu_local_state(void)
85{
86 return get_cpu_data(psci_svc_cpu_data.local_state);
87}
88
89static inline plat_local_state_t psci_get_cpu_local_state_by_idx(int idx)
90{
91 return get_cpu_data_by_index((unsigned int)idx,
92 psci_svc_cpu_data.local_state);
93}
94
95/* Helper function to identify a CPU standby request in PSCI Suspend call */
96static inline int is_cpu_standby_req(unsigned int is_power_down_state,
97 unsigned int retn_lvl)
98{
99 return ((is_power_down_state == 0U) && (retn_lvl == 0U)) ? 1 : 0;
100}
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000101
Achin Gupta4f6ad662013-10-25 09:08:21 +0100102/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100103 * The following two data structures implement the power domain tree. The tree
104 * is used to track the state of all the nodes i.e. power domain instances
105 * described by the platform. The tree consists of nodes that describe CPU power
106 * domains i.e. leaf nodes and all other power domains which are parents of a
107 * CPU power domain i.e. non-leaf nodes.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100108 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100109typedef struct non_cpu_pwr_domain_node {
110 /*
111 * Index of the first CPU power domain node level 0 which has this node
112 * as its parent.
113 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100114 int cpu_start_idx;
Soby Mathew981487a2015-07-13 14:10:57 +0100115
116 /*
117 * Number of CPU power domains which are siblings of the domain indexed
118 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
119 * -> cpu_start_idx + ncpus' have this node as their parent.
120 */
121 unsigned int ncpus;
122
123 /*
124 * Index of the parent power domain node.
125 * TODO: Figure out whether to whether using pointer is more efficient.
126 */
127 unsigned int parent_node;
128
129 plat_local_state_t local_state;
130
Achin Gupta75f73672013-12-05 16:33:10 +0000131 unsigned char level;
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100132
133 /* For indexing the psci_lock array*/
Soby Mathew981487a2015-07-13 14:10:57 +0100134 unsigned char lock_index;
Soby Mathew981487a2015-07-13 14:10:57 +0100135} non_cpu_pd_node_t;
136
137typedef struct cpu_pwr_domain_node {
Soby Mathew011ca182015-07-29 17:05:03 +0100138 u_register_t mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139
Soby Mathew981487a2015-07-13 14:10:57 +0100140 /*
141 * Index of the parent power domain node.
142 * TODO: Figure out whether to whether using pointer is more efficient.
143 */
144 unsigned int parent_node;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100145
Soby Mathew981487a2015-07-13 14:10:57 +0100146 /*
147 * A CPU power domain does not require state coordination like its
148 * parent power domains. Hence this node does not include a bakery
149 * lock. A spinlock is required by the CPU_ON handler to prevent a race
150 * when multiple CPUs try to turn ON the same target CPU.
151 */
152 spinlock_t cpu_lock;
153} cpu_pd_node_t;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100154
155/*******************************************************************************
Antonio Nino Diazdd0e85c2018-07-17 09:51:33 +0100156 * The following are helpers and declarations of locks.
157 ******************************************************************************/
158#if HW_ASSISTED_COHERENCY
159/*
160 * On systems where participant CPUs are cache-coherent, we can use spinlocks
161 * instead of bakery locks.
162 */
163#define DEFINE_PSCI_LOCK(_name) spinlock_t _name
164#define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name)
165
166/* One lock is required per non-CPU power domain node */
167DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
168
169/*
170 * On systems with hardware-assisted coherency, make PSCI cache operations NOP,
171 * as PSCI participants are cache-coherent, and there's no need for explicit
172 * cache maintenance operations or barriers to coordinate their state.
173 */
174static inline void psci_flush_dcache_range(uintptr_t __unused addr,
175 size_t __unused size)
176{
177 /* Empty */
178}
179
180#define psci_flush_cpu_data(member)
181#define psci_inv_cpu_data(member)
182
183static inline void psci_dsbish(void)
184{
185 /* Empty */
186}
187
188static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node)
189{
190 spin_lock(&psci_locks[non_cpu_pd_node->lock_index]);
191}
192
193static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node)
194{
195 spin_unlock(&psci_locks[non_cpu_pd_node->lock_index]);
196}
197
198#else /* if HW_ASSISTED_COHERENCY == 0 */
199/*
200 * Use bakery locks for state coordination as not all PSCI participants are
201 * cache coherent.
202 */
203#define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name)
204#define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name)
205
206/* One lock is required per non-CPU power domain node */
207DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
208
209/*
210 * If not all PSCI participants are cache-coherent, perform cache maintenance
211 * and issue barriers wherever required to coordinate state.
212 */
213static inline void psci_flush_dcache_range(uintptr_t addr, size_t size)
214{
215 flush_dcache_range(addr, size);
216}
217
218#define psci_flush_cpu_data(member) flush_cpu_data(member)
219#define psci_inv_cpu_data(member) inv_cpu_data(member)
220
221static inline void psci_dsbish(void)
222{
223 dsbish();
224}
225
226static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node)
227{
228 bakery_lock_get(&psci_locks[non_cpu_pd_node->lock_index]);
229}
230
231static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node)
232{
233 bakery_lock_release(&psci_locks[non_cpu_pd_node->lock_index]);
234}
235
236#endif /* HW_ASSISTED_COHERENCY */
237
238static inline void psci_lock_init(non_cpu_pd_node_t *non_cpu_pd_node,
239 unsigned char idx)
240{
241 non_cpu_pd_node[idx].lock_index = idx;
242}
243
244/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100245 * Data prototypes
246 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100247extern const plat_psci_ops_t *psci_plat_pm_ops;
248extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
249extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
Soby Mathew011ca182015-07-29 17:05:03 +0100250extern unsigned int psci_caps;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100251
252/*******************************************************************************
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000253 * SPD's power management hooks registered with PSCI
Achin Gupta607084e2014-02-09 18:24:19 +0000254 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100255extern const spd_pm_ops_t *psci_spd_pm;
Achin Gupta607084e2014-02-09 18:24:19 +0000256
257/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100258 * Function prototypes
259 ******************************************************************************/
260/* Private exported functions from psci_common.c */
Soby Mathew981487a2015-07-13 14:10:57 +0100261int psci_validate_power_state(unsigned int power_state,
262 psci_power_state_t *state_info);
263void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info);
Soby Mathew011ca182015-07-29 17:05:03 +0100264int psci_validate_mpidr(u_register_t mpidr);
Soby Mathew981487a2015-07-13 14:10:57 +0100265void psci_init_req_local_pwr_states(void);
Achin Gupta9b2bf252016-06-28 16:46:15 +0100266void psci_get_target_local_pwr_states(unsigned int end_pwrlvl,
267 psci_power_state_t *target_state);
Soby Mathewf1f97a12015-07-15 12:13:26 +0100268int psci_validate_entry_point(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100269 uintptr_t entrypoint, u_register_t context_id);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100270void psci_get_parent_pwr_domain_nodes(int cpu_idx,
Soby Mathew011ca182015-07-29 17:05:03 +0100271 unsigned int end_lvl,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100272 unsigned int *node_index);
Soby Mathew011ca182015-07-29 17:05:03 +0100273void psci_do_state_coordination(unsigned int end_pwrlvl,
Soby Mathew981487a2015-07-13 14:10:57 +0100274 psci_power_state_t *state_info);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100275void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx);
276void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, int cpu_idx);
Soby Mathew981487a2015-07-13 14:10:57 +0100277int psci_validate_suspend_req(const psci_power_state_t *state_info,
Roberto Vargas777dd432018-02-12 12:36:17 +0000278 unsigned int is_power_down_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100279unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info);
280unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info);
Soby Mathew011ca182015-07-29 17:05:03 +0100281void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl);
Soby Mathew981487a2015-07-13 14:10:57 +0100282void psci_print_power_domain_map(void);
Soby Mathew96168382014-12-17 14:47:57 +0000283unsigned int psci_is_last_on_cpu(void);
Soby Mathew011ca182015-07-29 17:05:03 +0100284int psci_spd_migrate_info(u_register_t *mpidr);
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000285void psci_do_pwrdown_sequence(unsigned int power_level);
286
287/*
288 * CPU power down is directly called only when HW_ASSISTED_COHERENCY is
289 * available. Otherwise, this needs post-call stack maintenance, which is
290 * handled in assembly.
291 */
292void prepare_cpu_pwr_dwn(unsigned int power_level);
Achin Gupta0959db52013-12-02 17:33:04 +0000293
Soby Mathew981487a2015-07-13 14:10:57 +0100294/* Private exported functions from psci_on.c */
Soby Mathewa0fedc42016-06-16 14:52:04 +0100295int psci_cpu_on_start(u_register_t target_cpu,
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100296 const entry_point_info_t *ep);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100297
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100298void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100299
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000300/* Private exported functions from psci_off.c */
Soby Mathew011ca182015-07-29 17:05:03 +0100301int psci_do_cpu_off(unsigned int end_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100302
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000303/* Private exported functions from psci_suspend.c */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100304void psci_cpu_suspend_start(const entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100305 unsigned int end_pwrlvl,
Soby Mathew981487a2015-07-13 14:10:57 +0100306 psci_power_state_t *state_info,
Roberto Vargas777dd432018-02-12 12:36:17 +0000307 unsigned int is_power_down_state);
Soby Mathew8595b872015-01-06 15:36:38 +0000308
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100309void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000310
Achin Guptae1aa5162014-06-26 09:58:52 +0100311/* Private exported functions from psci_helpers.S */
Soby Mathew011ca182015-07-29 17:05:03 +0100312void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level);
Achin Guptae1aa5162014-06-26 09:58:52 +0100313void psci_do_pwrup_cache_maintenance(void);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100314
Juan Castillo4dc4a472014-08-12 11:17:06 +0100315/* Private exported functions from psci_system_off.c */
316void __dead2 psci_system_off(void);
317void __dead2 psci_system_reset(void);
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100318u_register_t psci_system_reset2(uint32_t reset_type, u_register_t cookie);
Juan Castillo4dc4a472014-08-12 11:17:06 +0100319
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100320/* Private exported functions from psci_stat.c */
321void psci_stats_update_pwr_down(unsigned int end_pwrlvl,
322 const psci_power_state_t *state_info);
323void psci_stats_update_pwr_up(unsigned int end_pwrlvl,
dp-arm66abfbe2017-01-31 13:01:04 +0000324 const psci_power_state_t *state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100325u_register_t psci_stat_residency(u_register_t target_cpu,
326 unsigned int power_state);
327u_register_t psci_stat_count(u_register_t target_cpu,
328 unsigned int power_state);
329
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100330/* Private exported functions from psci_mem_protect.c */
Antonio Nino Diazf5c60012018-07-16 23:36:10 +0100331u_register_t psci_mem_protect(unsigned int enable);
332u_register_t psci_mem_chk_range(uintptr_t base, u_register_t length);
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100333
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100334#endif /* PSCI_PRIVATE_H */