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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Alexei Fedorov896799a2019-05-09 12:14:40 +01002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <common/tbbr/tbbr_img_def.h>
Alexei Fedorov896799a2019-05-09 12:14:40 +01008#include <drivers/arm/smmu_v3.h>
Aditya Angadi20b48412019-04-16 11:29:14 +05309#include <drivers/arm/sp805.h>
Alexei Fedorov896799a2019-05-09 12:14:40 +010010#include <plat/arm/common/arm_config.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000011#include <plat/arm/common/plat_arm.h>
Aditya Angadi20b48412019-04-16 11:29:14 +053012#include <plat/arm/common/arm_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <plat/common/platform.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010015
16/*******************************************************************************
17 * Perform any BL1 specific platform actions.
18 ******************************************************************************/
19void bl1_early_platform_setup(void)
20{
Dan Handley2b6b5742015-03-19 19:17:53 +000021 arm_bl1_early_platform_setup();
Sandrine Bailleuxe3060e22014-06-13 14:48:18 +010022
Harry Liebel30affd52013-10-30 17:41:48 +000023 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +010024 fvp_config_setup();
James Morrissey9d72b4e2014-02-10 17:04:32 +000025
Dan Handley2b6b5742015-03-19 19:17:53 +000026 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000027 * Initialize Interconnect for this cluster during cold boot.
Dan Handley2b6b5742015-03-19 19:17:53 +000028 * No need for locks as no other CPU is active.
29 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000030 fvp_interconnect_init();
Dan Handley2b6b5742015-03-19 19:17:53 +000031 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000032 * Enable coherency in Interconnect for the primary CPU's cluster.
Dan Handley2b6b5742015-03-19 19:17:53 +000033 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000034 fvp_interconnect_enable();
Vikram Kanigirida567432014-04-15 18:08:08 +010035}
Aditya Angadi20b48412019-04-16 11:29:14 +053036
37void plat_arm_secure_wdt_start(void)
38{
39 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
40}
41
42void plat_arm_secure_wdt_stop(void)
43{
44 sp805_stop(ARM_SP805_TWDG_BASE);
45}
Alexei Fedorov896799a2019-05-09 12:14:40 +010046
47void bl1_platform_setup(void)
48{
49 arm_bl1_platform_setup();
50
Alexei Fedorov7131d832019-08-16 14:15:59 +010051 /* Initialize System level generic or SP804 timer */
52 fvp_timer_init();
53
Alexei Fedorov896799a2019-05-09 12:14:40 +010054 /* On FVP RevC, initialize SMMUv3 */
55 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
56 smmuv3_security_init(PLAT_FVP_SMMUV3_BASE);
57}
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +010058
59__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
60{
61 /* Setup the watchdog to reset the system as soon as possible */
62 sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
63
64 while (1)
65 wfi();
66}