| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
| Bipin Ravi | 2f73d97 | 2022-01-20 00:01:04 -0600 | [diff] [blame] | 2 | * Copyright (c) 2021-2022, Arm Limited. All rights reserved. |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CORTEX_X2_H |
| 8 | #define CORTEX_X2_H |
| 9 | |
| 10 | #define CORTEX_X2_MIDR U(0x410FD480) |
| 11 | |
| Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 12 | /* Cortex-X2 loop count for CVE-2022-23960 mitigation */ |
| 13 | #define CORTEX_X2_BHB_LOOP_COUNT U(32) |
| 14 | |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions |
| 17 | ******************************************************************************/ |
| 18 | #define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 |
| Bipin Ravi | 2f73d97 | 2022-01-20 00:01:04 -0600 | [diff] [blame] | 19 | #define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 20 | |
| 21 | /******************************************************************************* |
| johpow01 | f6c37de | 2021-12-03 11:27:33 -0600 | [diff] [blame] | 22 | * CPU Extended Control register 2 specific definitions |
| 23 | ******************************************************************************/ |
| 24 | #define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5 |
| 25 | |
| 26 | #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11) |
| 27 | #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) |
| 28 | #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) |
| 29 | |
| 30 | /******************************************************************************* |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 31 | * CPU Power Control register specific definitions |
| 32 | ******************************************************************************/ |
| 33 | #define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 34 | #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 35 | |
| johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 36 | /******************************************************************************* |
| 37 | * CPU Auxiliary Control Register 5 definitions |
| 38 | ******************************************************************************/ |
| 39 | #define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 |
| Bipin Ravi | 78b7208 | 2022-02-06 01:29:31 -0600 | [diff] [blame] | 40 | #define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) |
| johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 41 | |
| Bipin Ravi | 9ad5478 | 2022-01-20 00:42:05 -0600 | [diff] [blame] | 42 | /******************************************************************************* |
| 43 | * CPU Implementation Specific Selected Instruction registers |
| 44 | ******************************************************************************/ |
| 45 | #define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 |
| 46 | #define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1 |
| 47 | #define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2 |
| 48 | #define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3 |
| 49 | |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 50 | #endif /* CORTEX_X2_H */ |