| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CORTEX_X2_H |
| 8 | #define CORTEX_X2_H |
| 9 | |
| 10 | #define CORTEX_X2_MIDR U(0x410FD480) |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * CPU Extended Control register specific definitions |
| 14 | ******************************************************************************/ |
| 15 | #define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 16 | |
| 17 | /******************************************************************************* |
| 18 | * CPU Power Control register specific definitions |
| 19 | ******************************************************************************/ |
| 20 | #define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 21 | #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 22 | |
| johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame^] | 23 | /******************************************************************************* |
| 24 | * CPU Auxiliary Control Register 5 definitions |
| 25 | ******************************************************************************/ |
| 26 | #define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 |
| 27 | |
| johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 28 | #endif /* CORTEX_X2_H */ |