fix(errata): workaround for Cortex X2 erratum 2058056
Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.
There are 2 ways this workaround can be accomplished, the first of
which involves executing a few additional instructions around MSR
writes to CPUECTLR when disabling the prefetcher. (see SDEN for
details)
However, this patch implements the 2nd possible workaround which sets
the prefetcher into its most conservative mode, since this workaround
is generic.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3
diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h
index 3c315d5..bf1b460 100644
--- a/include/lib/cpus/aarch64/cortex_x2.h
+++ b/include/lib/cpus/aarch64/cortex_x2.h
@@ -15,6 +15,15 @@
#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
+ * CPU Extended Control register 2 specific definitions
+ ******************************************************************************/
+#define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5
+
+#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11)
+#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
+#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
+
+/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7