blob: 3df8f07eb02be72e1e77c9d103ca1211e1415e38 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Zelalem Aweke688fbf72021-07-09 11:37:10 -05002 * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Masahiro Yamada0b67e562020-03-09 17:39:48 +09007#include <common/bl_common.ld.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <lib/xlat_tables/xlat_tables_defs.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000012ENTRY(bl2_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010013
14MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010015 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010016}
17
Chris Kay4b7660a2022-09-29 14:36:53 +010018SECTIONS {
Achin Gupta4f6ad662013-10-25 09:08:21 +010019 . = BL2_BASE;
Chris Kay4b7660a2022-09-29 14:36:53 +010020
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000021 ASSERT(. == ALIGN(PAGE_SIZE),
Chris Kay4b7660a2022-09-29 14:36:53 +010022 "BL2_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010023
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010024#if SEPARATE_CODE_AND_RODATA
25 .text . : {
26 __TEXT_START__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010027
Zelalem Aweke688fbf72021-07-09 11:37:10 -050028#if ENABLE_RME
29 *bl2_rme_entrypoint.o(.text*)
30#else /* ENABLE_RME */
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010031 *bl2_entrypoint.o(.text*)
Zelalem Aweke688fbf72021-07-09 11:37:10 -050032#endif /* ENABLE_RME */
Chris Kay4b7660a2022-09-29 14:36:53 +010033
Samuel Holland23f5e542019-10-20 16:11:25 -050034 *(SORT_BY_ALIGNMENT(.text*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010035 *(.vectors)
Chris Kay4b7660a2022-09-29 14:36:53 +010036
Roberto Vargasd93fde32018-04-11 11:53:31 +010037 . = ALIGN(PAGE_SIZE);
Chris Kay4b7660a2022-09-29 14:36:53 +010038
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010039 __TEXT_END__ = .;
Jorge Troncosoda284d52022-10-20 21:42:06 -070040 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010041
Chris Kay4b7660a2022-09-29 14:36:53 +010042 /* .ARM.extab and .ARM.exidx are only added because Clang needs them */
Jorge Troncosoda284d52022-10-20 21:42:06 -070043 .ARM.extab . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010044 *(.ARM.extab* .gnu.linkonce.armextab.*)
Jorge Troncosoda284d52022-10-20 21:42:06 -070045 } >RAM
Roberto Vargas1d04c632018-05-10 11:01:16 +010046
Jorge Troncosoda284d52022-10-20 21:42:06 -070047 .ARM.exidx . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010048 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
Jorge Troncosoda284d52022-10-20 21:42:06 -070049 } >RAM
Roberto Vargas1d04c632018-05-10 11:01:16 +010050
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010051 .rodata . : {
52 __RODATA_START__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010053
Samuel Holland23f5e542019-10-20 16:11:25 -050054 *(SORT_BY_ALIGNMENT(.rodata*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010055
Chris Kay4b7660a2022-09-29 14:36:53 +010056 RODATA_COMMON
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010057
Roberto Vargasd93fde32018-04-11 11:53:31 +010058 . = ALIGN(PAGE_SIZE);
Chris Kay4b7660a2022-09-29 14:36:53 +010059
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010060 __RODATA_END__ = .;
61 } >RAM
Chris Kay4b7660a2022-09-29 14:36:53 +010062#else /* SEPARATE_CODE_AND_RODATA */
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000063 ro . : {
64 __RO_START__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010065
Andrew Thoelkee01ea342014-03-18 07:13:52 +000066 *bl2_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050067 *(SORT_BY_ALIGNMENT(.text*))
68 *(SORT_BY_ALIGNMENT(.rodata*))
Juan Castillo8e55d932015-04-02 09:48:16 +010069
Chris Kay4b7660a2022-09-29 14:36:53 +010070 RODATA_COMMON
Juan Castillo8e55d932015-04-02 09:48:16 +010071
Achin Guptab739f222014-01-18 16:50:09 +000072 *(.vectors)
Chris Kay4b7660a2022-09-29 14:36:53 +010073
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000074 __RO_END_UNALIGNED__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +010075
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000076 /*
Chris Kay4b7660a2022-09-29 14:36:53 +010077 * Memory page(s) mapped to this section will be marked as read-only,
78 * executable. No RW data from the next section must creep in. Ensure
79 * that the rest of the current memory page is unused.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000080 */
Roberto Vargasd93fde32018-04-11 11:53:31 +010081 . = ALIGN(PAGE_SIZE);
Chris Kay4b7660a2022-09-29 14:36:53 +010082
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000083 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010084 } >RAM
Chris Kay4b7660a2022-09-29 14:36:53 +010085#endif /* SEPARATE_CODE_AND_RODATA */
Achin Gupta4f6ad662013-10-25 09:08:21 +010086
Chris Kay4b7660a2022-09-29 14:36:53 +010087 __RW_START__ = .;
Achin Guptae9c4a642015-09-11 16:03:13 +010088
Masahiro Yamadac5864d82020-04-22 10:50:12 +090089 DATA_SECTION >RAM
Masahiro Yamada403990e2020-04-07 13:04:24 +090090 STACK_SECTION >RAM
Masahiro Yamadadd053b62020-03-26 13:16:33 +090091 BSS_SECTION >RAM
Masahiro Yamada0b67e562020-03-09 17:39:48 +090092 XLAT_TABLE_SECTION >RAM
Achin Guptaa0cd9892014-02-09 13:30:38 +000093
Soby Mathew2ae20432015-01-08 18:02:44 +000094#if USE_COHERENT_MEM
Achin Guptaa0cd9892014-02-09 13:30:38 +000095 /*
Chris Kay4b7660a2022-09-29 14:36:53 +010096 * The base address of the coherent memory section must be page-aligned to
97 * guarantee that the coherent data are stored on their own pages and are
98 * not mixed with normal data. This is required to set up the correct
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000099 * memory attributes for the coherent data page tables.
100 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000101 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000102 __COHERENT_RAM_START__ = .;
103 *(tzfw_coherent_mem)
104 __COHERENT_RAM_END_UNALIGNED__ = .;
Chris Kay4b7660a2022-09-29 14:36:53 +0100105
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000106 /*
Chris Kay4b7660a2022-09-29 14:36:53 +0100107 * Memory page(s) mapped to this section will be marked as device
108 * memory. No other unexpected data must creep in. Ensure the rest of
109 * the current memory page is unused.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000110 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100111 . = ALIGN(PAGE_SIZE);
Chris Kay4b7660a2022-09-29 14:36:53 +0100112
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000113 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100114 } >RAM
Chris Kay4b7660a2022-09-29 14:36:53 +0100115#endif /* USE_COHERENT_MEM */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116
Achin Guptae9c4a642015-09-11 16:03:13 +0100117 __RW_END__ = .;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000118 __BL2_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100119
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000120 __BSS_SIZE__ = SIZEOF(.bss);
Soby Mathew2ae20432015-01-08 18:02:44 +0000121
122#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000123 __COHERENT_RAM_UNALIGNED_SIZE__ =
124 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Chris Kay4b7660a2022-09-29 14:36:53 +0100125#endif /* USE_COHERENT_MEM */
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100126
127 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128}