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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Zelalem Aweke688fbf72021-07-09 11:37:10 -05002 * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Masahiro Yamada0b67e562020-03-09 17:39:48 +09007#include <common/bl_common.ld.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <lib/xlat_tables/xlat_tables_defs.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000012ENTRY(bl2_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010013
14MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010015 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010016}
17
18
19SECTIONS
20{
21 . = BL2_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000022 ASSERT(. == ALIGN(PAGE_SIZE),
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000023 "BL2_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010024
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010025#if SEPARATE_CODE_AND_RODATA
26 .text . : {
27 __TEXT_START__ = .;
Zelalem Aweke688fbf72021-07-09 11:37:10 -050028#if ENABLE_RME
29 *bl2_rme_entrypoint.o(.text*)
30#else /* ENABLE_RME */
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010031 *bl2_entrypoint.o(.text*)
Zelalem Aweke688fbf72021-07-09 11:37:10 -050032#endif /* ENABLE_RME */
Samuel Holland23f5e542019-10-20 16:11:25 -050033 *(SORT_BY_ALIGNMENT(.text*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010034 *(.vectors)
Roberto Vargasd93fde32018-04-11 11:53:31 +010035 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010036 __TEXT_END__ = .;
Jorge Troncosoda284d52022-10-20 21:42:06 -070037 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010038
Jorge Troncosoda284d52022-10-20 21:42:06 -070039 /* .ARM.extab and .ARM.exidx are only added because Clang need them */
40 .ARM.extab . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010041 *(.ARM.extab* .gnu.linkonce.armextab.*)
Jorge Troncosoda284d52022-10-20 21:42:06 -070042 } >RAM
Roberto Vargas1d04c632018-05-10 11:01:16 +010043
Jorge Troncosoda284d52022-10-20 21:42:06 -070044 .ARM.exidx . : {
Roberto Vargas1d04c632018-05-10 11:01:16 +010045 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
Jorge Troncosoda284d52022-10-20 21:42:06 -070046 } >RAM
Roberto Vargas1d04c632018-05-10 11:01:16 +010047
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010048 .rodata . : {
49 __RODATA_START__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -050050 *(SORT_BY_ALIGNMENT(.rodata*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010051
Masahiro Yamada583f8dd2020-03-26 10:57:12 +090052 RODATA_COMMON
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010053
Roberto Vargasd93fde32018-04-11 11:53:31 +010054 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010055 __RODATA_END__ = .;
56 } >RAM
57#else
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000058 ro . : {
59 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000060 *bl2_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050061 *(SORT_BY_ALIGNMENT(.text*))
62 *(SORT_BY_ALIGNMENT(.rodata*))
Juan Castillo8e55d932015-04-02 09:48:16 +010063
Masahiro Yamada583f8dd2020-03-26 10:57:12 +090064 RODATA_COMMON
Juan Castillo8e55d932015-04-02 09:48:16 +010065
Achin Guptab739f222014-01-18 16:50:09 +000066 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000067 __RO_END_UNALIGNED__ = .;
68 /*
69 * Memory page(s) mapped to this section will be marked as
70 * read-only, executable. No RW data from the next section must
71 * creep in. Ensure the rest of the current memory page is unused.
72 */
Roberto Vargasd93fde32018-04-11 11:53:31 +010073 . = ALIGN(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000074 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010075 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010076#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010077
Achin Guptae9c4a642015-09-11 16:03:13 +010078 /*
79 * Define a linker symbol to mark start of the RW memory area for this
80 * image.
81 */
82 __RW_START__ = . ;
83
Masahiro Yamadac5864d82020-04-22 10:50:12 +090084 DATA_SECTION >RAM
Masahiro Yamada403990e2020-04-07 13:04:24 +090085 STACK_SECTION >RAM
Masahiro Yamadadd053b62020-03-26 13:16:33 +090086 BSS_SECTION >RAM
Masahiro Yamada0b67e562020-03-09 17:39:48 +090087 XLAT_TABLE_SECTION >RAM
Achin Guptaa0cd9892014-02-09 13:30:38 +000088
Soby Mathew2ae20432015-01-08 18:02:44 +000089#if USE_COHERENT_MEM
Achin Guptaa0cd9892014-02-09 13:30:38 +000090 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000091 * The base address of the coherent memory section must be page-aligned (4K)
92 * to guarantee that the coherent data are stored on their own pages and
93 * are not mixed with normal data. This is required to set up the correct
94 * memory attributes for the coherent data page tables.
95 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000096 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000097 __COHERENT_RAM_START__ = .;
98 *(tzfw_coherent_mem)
99 __COHERENT_RAM_END_UNALIGNED__ = .;
100 /*
101 * Memory page(s) mapped to this section will be marked
102 * as device memory. No other unexpected data must creep in.
103 * Ensure the rest of the current memory page is unused.
104 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100105 . = ALIGN(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000106 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107 } >RAM
Soby Mathew2ae20432015-01-08 18:02:44 +0000108#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100109
Achin Guptae9c4a642015-09-11 16:03:13 +0100110 /*
111 * Define a linker symbol to mark end of the RW memory area for this
112 * image.
113 */
114 __RW_END__ = .;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000115 __BL2_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000117 __BSS_SIZE__ = SIZEOF(.bss);
Soby Mathew2ae20432015-01-08 18:02:44 +0000118
119#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000120 __COHERENT_RAM_UNALIGNED_SIZE__ =
121 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Soby Mathew2ae20432015-01-08 18:02:44 +0000122#endif
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100123
124 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100125}