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Oliver Swede8fed2fe2019-11-11 11:11:06 +00001#
Daniel Boulby941a9092023-05-10 14:42:43 +01002# Copyright (c) 2021-2023, Arm Limited. All rights reserved.
Oliver Swede8fed2fe2019-11-11 11:11:06 +00003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Chris Kaye9272152021-09-28 15:52:14 +01007include common/fdt_wrappers.mk
Andre Przywaraeec45eb2020-01-24 15:02:27 +00008include lib/libfdt/libfdt.mk
9
Oliver Swede8fed2fe2019-11-11 11:11:06 +000010RESET_TO_BL31 := 1
11ifeq (${RESET_TO_BL31}, 0)
12$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
13endif
14
Oliver Swede3769b3f2019-12-16 14:08:27 +000015ifeq (${ENABLE_PIE}, 1)
16override SEPARATE_CODE_AND_RODATA := 1
17endif
18
Oliver Swede8fed2fe2019-11-11 11:11:06 +000019CTX_INCLUDE_AARCH32_REGS := 0
20ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
21$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
22endif
23
24ifeq (${TRUSTED_BOARD_BOOT}, 1)
25$(error "TRUSTED_BOARD_BOOT must be disabled")
26endif
27
Andre Przywarad9b95cc2020-07-08 13:01:00 +010028PRELOADED_BL33_BASE := 0x80080000
Oliver Swede8fed2fe2019-11-11 11:11:06 +000029
Andre Przywarad9b95cc2020-07-08 13:01:00 +010030FPGA_PRELOADED_DTB_BASE := 0x80070000
Oliver Swede8fed2fe2019-11-11 11:11:06 +000031$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
Oliver Swede8fed2fe2019-11-11 11:11:06 +000032
Andre Przywara01767932020-07-07 10:40:46 +010033FPGA_PRELOADED_CMD_LINE := 0x1000
34$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE))
35
Andre Przywara480e5942023-08-31 15:47:54 +010036ENABLE_BRBE_FOR_NS := 2
37ENABLE_TRBE_FOR_NS := 2
38ENABLE_FEAT_AMU := 2
39ENABLE_FEAT_AMUv1p1 := 2
40ENABLE_FEAT_CSV2_2 := 2
41ENABLE_FEAT_ECV := 2
42ENABLE_FEAT_FGT := 2
43ENABLE_FEAT_HCX := 2
Andre Przywara480e5942023-08-31 15:47:54 +010044ENABLE_SYS_REG_TRACE_FOR_NS := 2
45ENABLE_TRF_FOR_NS := 2
Tom Cosgrove2593a8a2021-08-17 08:50:53 +010046
Oliver Swede8fed2fe2019-11-11 11:11:06 +000047# Treating this as a memory-constrained port for now
48USE_COHERENT_MEM := 0
49
Oliver Swede7fbb9b52020-01-15 10:20:09 +000050# This can be overridden depending on CPU(s) used in the FPGA image
Oliver Swede8fed2fe2019-11-11 11:11:06 +000051HW_ASSISTED_COHERENCY := 1
52
Andre Przywara8b505252020-04-09 10:10:09 +010053PL011_GENERIC_UART := 1
54
Javier Almansa Sobrinoe1ecd232020-08-20 18:48:09 +010055SUPPORT_UNKNOWN_MPID ?= 1
56
Oliver Swede7fbb9b52020-01-15 10:20:09 +000057FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
58
59# select a different set of CPU files, depending on whether we compile for
60# hardware assisted coherency cores or not
61ifeq (${HW_ASSISTED_COHERENCY}, 0)
62# Cores used without DSU
63 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
64 lib/cpus/aarch64/cortex_a53.S \
65 lib/cpus/aarch64/cortex_a57.S \
66 lib/cpus/aarch64/cortex_a72.S \
67 lib/cpus/aarch64/cortex_a73.S
68else
69# AArch64-only cores
Govindraj Raja0a120912023-06-23 11:09:31 -050070 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \
Govindraj Rajaca3caf02023-06-28 08:49:21 -050071 lib/cpus/aarch64/cortex_a520.S \
Govindraj Raja0a120912023-06-23 11:09:31 -050072 lib/cpus/aarch64/cortex_a715.S \
Govindraj Raja37012fb2023-06-23 11:28:05 -050073 lib/cpus/aarch64/cortex_a720.S \
Govindraj Raja0a120912023-06-23 11:09:31 -050074 lib/cpus/aarch64/cortex_x3.S \
75 lib/cpus/aarch64/cortex_x4.S \
Daniel Boulby941a9092023-05-10 14:42:43 +010076 lib/cpus/aarch64/neoverse_n_common.S \
Govindraj Raja0a120912023-06-23 11:09:31 -050077 lib/cpus/aarch64/neoverse_n1.S \
78 lib/cpus/aarch64/neoverse_n2.S \
79 lib/cpus/aarch64/neoverse_v1.S \
Govindraj Raja0a120912023-06-23 11:09:31 -050080 lib/cpus/aarch64/cortex_chaberton.S \
Daniel Boulby941a9092023-05-10 14:42:43 +010081 lib/cpus/aarch64/cortex_blackhawk.S
Andre Przywaracb167672020-06-25 13:10:38 +010082
Oliver Swede7fbb9b52020-01-15 10:20:09 +000083# AArch64/AArch32 cores
84 FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
85 lib/cpus/aarch64/cortex_a75.S
86endif
Oliver Swede8fed2fe2019-11-11 11:11:06 +000087
Javier Almansa Sobrinoe1ecd232020-08-20 18:48:09 +010088ifeq (${SUPPORT_UNKNOWN_MPID}, 1)
89# Add support for unknown/invalid MPIDs (aarch64 only)
90$(eval $(call add_define,SUPPORT_UNKNOWN_MPID))
91 FPGA_CPU_LIBS += lib/cpus/aarch64/generic.S
92endif
93
Andre Przywarae1cc1302020-03-25 15:50:38 +000094# Allow detection of GIC-600
95GICV3_SUPPORT_GIC600 := 1
Manish Pandeyb21cad72020-04-03 18:59:20 +010096
Andre Przywara42ba7c92021-05-18 15:53:05 +010097GIC_ENABLE_V4_EXTN := 1
98
Manish Pandeyb21cad72020-04-03 18:59:20 +010099# Include GICv3 driver files
100include drivers/arm/gic/v3/gicv3.mk
101
102FPGA_GIC_SOURCES := ${GICV3_SOURCES} \
Oliver Swedeb51da812019-12-03 14:08:21 +0000103 plat/common/plat_gicv3.c \
104 plat/arm/board/arm_fpga/fpga_gicv3.c
Oliver Swede8fed2fe2019-11-11 11:11:06 +0000105
Andre Przywaraeb5cb802020-08-03 12:54:58 +0100106FDT_SOURCES := fdts/arm_fpga.dts
107
Oliver Swede8fed2fe2019-11-11 11:11:06 +0000108PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
109
110PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
111
Chris Kaye9272152021-09-28 15:52:14 +0100112BL31_SOURCES += common/fdt_fixup.c \
Andre Przywaraeec45eb2020-01-24 15:02:27 +0000113 drivers/delay_timer/delay_timer.c \
Oliver Swede8fed2fe2019-11-11 11:11:06 +0000114 drivers/delay_timer/generic_delay_timer.c \
115 drivers/arm/pl011/${ARCH}/pl011_console.S \
116 plat/common/plat_psci_common.c \
117 plat/arm/board/arm_fpga/fpga_pm.c \
118 plat/arm/board/arm_fpga/fpga_topology.c \
119 plat/arm/board/arm_fpga/fpga_console.c \
120 plat/arm/board/arm_fpga/fpga_bl31_setup.c \
121 ${FPGA_CPU_LIBS} \
122 ${FPGA_GIC_SOURCES}
123
Chris Kaye9272152021-09-28 15:52:14 +0100124BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
125
Andre Przywara45e794f2021-10-07 14:19:12 +0100126$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,bl31))
127$(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/kernel_trampoline.S,bl31))
128$(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,bl31))
Andre Przywara6228e432020-09-16 17:13:33 +0100129
Andre Przywara8c6d92d2021-05-14 16:13:28 +0100130bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/kernel_trampoline.o ${BUILD_PLAT}/build_axf.ld
Andre Przywara6228e432020-09-16 17:13:33 +0100131 $(ECHO) " LD $@"
Andre Przywara4d8a6bb2021-08-20 16:23:23 +0100132 $(Q)$(LD) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} --strip-debug -s -n -o ${BUILD_PLAT}/bl31.axf
Andre Przywara586de5e2020-08-03 13:06:38 +0100133
Andre Przywara6228e432020-09-16 17:13:33 +0100134all: bl31.axf