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Soby Mathew991d42c2015-06-29 16:30:12 +01001/*
Soby Mathew0d786072016-03-24 16:56:29 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Soby Mathew991d42c2015-06-29 16:30:12 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arch_helpers.h>
33#include <assert.h>
34#include <bl_common.h>
Soby Mathew991d42c2015-06-29 16:30:12 +010035#include <debug.h>
36#include <context_mgmt.h>
37#include <platform.h>
Soby Mathew991d42c2015-06-29 16:30:12 +010038#include <stddef.h>
39#include "psci_private.h"
40
Soby Mathew991d42c2015-06-29 16:30:12 +010041/*******************************************************************************
42 * This function checks whether a cpu which has been requested to be turned on
43 * is OFF to begin with.
44 ******************************************************************************/
Soby Mathew85dbf5a2015-04-07 12:16:56 +010045static int cpu_on_validate_state(aff_info_state_t aff_state)
Soby Mathew991d42c2015-06-29 16:30:12 +010046{
Soby Mathew85dbf5a2015-04-07 12:16:56 +010047 if (aff_state == AFF_STATE_ON)
Soby Mathew991d42c2015-06-29 16:30:12 +010048 return PSCI_E_ALREADY_ON;
49
Soby Mathew85dbf5a2015-04-07 12:16:56 +010050 if (aff_state == AFF_STATE_ON_PENDING)
Soby Mathew991d42c2015-06-29 16:30:12 +010051 return PSCI_E_ON_PENDING;
52
Soby Mathew85dbf5a2015-04-07 12:16:56 +010053 assert(aff_state == AFF_STATE_OFF);
Soby Mathew991d42c2015-06-29 16:30:12 +010054 return PSCI_E_SUCCESS;
55}
56
57/*******************************************************************************
Soby Mathew991d42c2015-06-29 16:30:12 +010058 * Generic handler which is called to physically power on a cpu identified by
Soby Mathew6b8b3022015-06-30 11:00:24 +010059 * its mpidr. It performs the generic, architectural, platform setup and state
60 * management to power on the target cpu e.g. it will ensure that
61 * enough information is stashed for it to resume execution in the non-secure
62 * security state.
Soby Mathew991d42c2015-06-29 16:30:12 +010063 *
Soby Mathew3a9e8bf2015-05-05 16:33:16 +010064 * The state of all the relevant power domains are changed after calling the
Soby Mathew6b8b3022015-06-30 11:00:24 +010065 * platform handler as it can return error.
Soby Mathew991d42c2015-06-29 16:30:12 +010066 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010067int psci_cpu_on_start(u_register_t target_cpu,
Sandrine Bailleux7497bff2016-04-25 09:28:43 +010068 entry_point_info_t *ep)
Soby Mathew991d42c2015-06-29 16:30:12 +010069{
70 int rc;
Soby Mathew9d754f62015-04-08 17:42:06 +010071 unsigned int target_idx = plat_core_pos_by_mpidr(target_cpu);
Soby Mathewca370502016-01-26 11:47:53 +000072 aff_info_state_t target_aff_state;
Soby Mathew991d42c2015-06-29 16:30:12 +010073
Sandrine Bailleux6181acb2016-04-22 13:00:19 +010074 /* Calling function must supply valid input arguments */
75 assert((int) target_idx >= 0);
76 assert(ep != NULL);
77
Soby Mathew991d42c2015-06-29 16:30:12 +010078 /*
79 * This function must only be called on platforms where the
80 * CPU_ON platform hooks have been implemented.
81 */
Soby Mathew3a9e8bf2015-05-05 16:33:16 +010082 assert(psci_plat_pm_ops->pwr_domain_on &&
83 psci_plat_pm_ops->pwr_domain_on_finish);
Soby Mathew991d42c2015-06-29 16:30:12 +010084
Soby Mathew9d754f62015-04-08 17:42:06 +010085 /* Protect against multiple CPUs trying to turn ON the same target CPU */
86 psci_spin_lock_cpu(target_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +010087
88 /*
Soby Mathew991d42c2015-06-29 16:30:12 +010089 * Generic management: Ensure that the cpu is off to be
90 * turned on.
91 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +010092 rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx));
Soby Mathew991d42c2015-06-29 16:30:12 +010093 if (rc != PSCI_E_SUCCESS)
94 goto exit;
95
96 /*
97 * Call the cpu on handler registered by the Secure Payload Dispatcher
98 * to let it do any bookeeping. If the handler encounters an error, it's
99 * expected to assert within
100 */
101 if (psci_spd_pm && psci_spd_pm->svc_on)
102 psci_spd_pm->svc_on(target_cpu);
103
104 /*
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100105 * Set the Affinity info state of the target cpu to ON_PENDING.
Soby Mathewca370502016-01-26 11:47:53 +0000106 * Flush aff_info_state as it will be accessed with caches
107 * turned OFF.
Soby Mathew991d42c2015-06-29 16:30:12 +0100108 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100109 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
Soby Mathewca370502016-01-26 11:47:53 +0000110 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state);
111
112 /*
113 * The cache line invalidation by the target CPU after setting the
114 * state to OFF (see psci_do_cpu_off()), could cause the update to
115 * aff_info_state to be invalidated. Retry the update if the target
116 * CPU aff_info_state is not ON_PENDING.
117 */
118 target_aff_state = psci_get_aff_info_state_by_idx(target_idx);
119 if (target_aff_state != AFF_STATE_ON_PENDING) {
120 assert(target_aff_state == AFF_STATE_OFF);
121 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
122 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state);
123
124 assert(psci_get_aff_info_state_by_idx(target_idx) == AFF_STATE_ON_PENDING);
125 }
Soby Mathew6b8b3022015-06-30 11:00:24 +0100126
127 /*
128 * Perform generic, architecture and platform specific handling.
129 */
Soby Mathew6b8b3022015-06-30 11:00:24 +0100130 /*
131 * Plat. management: Give the platform the current state
132 * of the target cpu to allow it to perform the necessary
133 * steps to power on.
134 */
Soby Mathew011ca182015-07-29 17:05:03 +0100135 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu);
Soby Mathew991d42c2015-06-29 16:30:12 +0100136 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
137
138 if (rc == PSCI_E_SUCCESS)
139 /* Store the re-entry information for the non-secure world. */
Soby Mathewb0082d22015-04-09 13:40:55 +0100140 cm_init_context_by_index(target_idx, ep);
Soby Mathewca370502016-01-26 11:47:53 +0000141 else {
Soby Mathew991d42c2015-06-29 16:30:12 +0100142 /* Restore the state on error. */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100143 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF);
Soby Mathewca370502016-01-26 11:47:53 +0000144 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state);
145 }
Soby Mathewb0082d22015-04-09 13:40:55 +0100146
Soby Mathew991d42c2015-06-29 16:30:12 +0100147exit:
Soby Mathew9d754f62015-04-08 17:42:06 +0100148 psci_spin_unlock_cpu(target_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +0100149 return rc;
150}
151
152/*******************************************************************************
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100153 * The following function finish an earlier power on request. They
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100154 * are called by the common finisher routine in psci_common.c. The `state_info`
155 * is the psci_power_state from which this CPU has woken up from.
Soby Mathew991d42c2015-06-29 16:30:12 +0100156 ******************************************************************************/
Soby Mathew9d754f62015-04-08 17:42:06 +0100157void psci_cpu_on_finish(unsigned int cpu_idx,
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100158 psci_power_state_t *state_info)
Soby Mathew991d42c2015-06-29 16:30:12 +0100159{
Soby Mathew991d42c2015-06-29 16:30:12 +0100160 /*
161 * Plat. management: Perform the platform specific actions
162 * for this cpu e.g. enabling the gic or zeroing the mailbox
163 * register. The actual state of this cpu has already been
164 * changed.
165 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100166 psci_plat_pm_ops->pwr_domain_on_finish(state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100167
168 /*
169 * Arch. management: Enable data cache and manage stack memory
170 */
171 psci_do_pwrup_cache_maintenance();
172
173 /*
174 * All the platform specific actions for turning this cpu
175 * on have completed. Perform enough arch.initialization
176 * to run in the non-secure address space.
177 */
Soby Mathewd0194872016-04-29 19:01:30 +0100178 psci_arch_setup();
Soby Mathew991d42c2015-06-29 16:30:12 +0100179
180 /*
Soby Mathew9d754f62015-04-08 17:42:06 +0100181 * Lock the CPU spin lock to make sure that the context initialization
182 * is done. Since the lock is only used in this function to create
183 * a synchronization point with cpu_on_start(), it can be released
184 * immediately.
185 */
186 psci_spin_lock_cpu(cpu_idx);
187 psci_spin_unlock_cpu(cpu_idx);
188
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100189 /* Ensure we have been explicitly woken up by another cpu */
190 assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING);
191
Soby Mathew9d754f62015-04-08 17:42:06 +0100192 /*
Soby Mathew991d42c2015-06-29 16:30:12 +0100193 * Call the cpu on finish handler registered by the Secure Payload
194 * Dispatcher to let it do any bookeeping. If the handler encounters an
195 * error, it's expected to assert within
196 */
197 if (psci_spd_pm && psci_spd_pm->svc_on_finish)
198 psci_spd_pm->svc_on_finish(0);
199
Soby Mathew9d754f62015-04-08 17:42:06 +0100200 /* Populate the mpidr field within the cpu node array */
201 /* This needs to be done only once */
202 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK;
203
Soby Mathew991d42c2015-06-29 16:30:12 +0100204 /*
205 * Generic management: Now we just need to retrieve the
206 * information that we had stashed away during the cpu_on
207 * call to set this cpu on its way.
208 */
209 cm_prepare_el3_exit(NON_SECURE);
Soby Mathew991d42c2015-06-29 16:30:12 +0100210}