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Ryan Harkin25cff832014-01-13 12:37:03 +00001#
johpow01aef12f22020-10-15 13:40:04 -05002# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
Ryan Harkin25cff832014-01-13 12:37:03 +00003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Ryan Harkin25cff832014-01-13 12:37:03 +00005#
6
Soby Mathewb6f3b1f2016-04-07 17:40:04 +01007# Use the GICv3 driver on the FVP by default
8FVP_USE_GIC_DRIVER := FVP_GICV3
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +00009
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000010# Default cluster count for FVP
11FVP_CLUSTER_COUNT := 2
12
Jeenu Viswambharan75421132018-01-31 14:52:08 +000013# Default number of CPUs per cluster on FVP
14FVP_MAX_CPUS_PER_CLUSTER := 4
15
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000016# Default number of threads per CPU on FVP
17FVP_MAX_PE_PER_CPU := 1
18
Manish V Badarkheb24c6372021-01-24 03:26:50 +000019# Disable redistributor frame of inactive/fused CPU cores by marking it as read
20# only; enable redistributor frames of all CPU cores by default.
21FVP_GICR_REGION_PROTECTION := 0
22
Soby Mathew5f6412a2018-02-08 11:39:38 +000023FVP_DT_PREFIX := fvp-base-gicv3-psci
24
Achin Gupta1fa7eb62015-11-03 14:18:34 +000025# The FVP platform depends on this macro to build with correct GIC driver.
26$(eval $(call add_define,FVP_USE_GIC_DRIVER))
27
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000028# Pass FVP_CLUSTER_COUNT to the build system.
Soby Mathew47e43f22016-02-01 14:04:34 +000029$(eval $(call add_define,FVP_CLUSTER_COUNT))
Soby Mathew7356b1e2016-03-24 10:12:42 +000030
Jeenu Viswambharan75421132018-01-31 14:52:08 +000031# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system.
32$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER))
33
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000034# Pass FVP_MAX_PE_PER_CPU to the build system.
35$(eval $(call add_define,FVP_MAX_PE_PER_CPU))
36
Manish V Badarkheb24c6372021-01-24 03:26:50 +000037# Pass FVP_GICR_REGION_PROTECTION to the build system.
38$(eval $(call add_define,FVP_GICR_REGION_PROTECTION))
39
Soby Mathew7356b1e2016-03-24 10:12:42 +000040# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2,
41# choose the CCI driver , else the CCN driver
42ifeq ($(FVP_CLUSTER_COUNT), 0)
43$(error "Incorrect cluster count specified for FVP port")
44else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2))
45FVP_INTERCONNECT_DRIVER := FVP_CCI
46else
47FVP_INTERCONNECT_DRIVER := FVP_CCN
Soby Mathew47e43f22016-02-01 14:04:34 +000048endif
49
Soby Mathew7356b1e2016-03-24 10:12:42 +000050$(eval $(call add_define,FVP_INTERCONNECT_DRIVER))
51
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +000052# Choose the GIC sources depending upon the how the FVP will be invoked
Andre Przywarae1cc1302020-03-25 15:50:38 +000053ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3)
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +000054
Andre Przywarae1cc1302020-03-25 15:50:38 +000055# The GIC model (GIC-600 or GIC-500) will be detected at runtime
56GICV3_SUPPORT_GIC600 := 1
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +000057GICV3_OVERRIDE_DISTIF_PWR_OPS := 1
58
59# Include GICv3 driver files
60include drivers/arm/gic/v3/gicv3.mk
61
62FVP_GIC_SOURCES := ${GICV3_SOURCES} \
Achin Gupta1fa7eb62015-11-03 14:18:34 +000063 plat/common/plat_gicv3.c \
64 plat/arm/common/arm_gicv3.c
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +000065
laurenw-armdc5e9a22020-05-12 10:58:11 -050066 ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),)
67 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
68 endif
69
Achin Gupta1fa7eb62015-11-03 14:18:34 +000070else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
Alexei Fedorovfc4f80e2020-04-07 11:48:00 +010071
72# No GICv4 extension
73GIC_ENABLE_V4_EXTN := 0
74$(eval $(call add_define,GIC_ENABLE_V4_EXTN))
75
Alexei Fedorovcaa18022020-07-14 10:47:25 +010076# Include GICv2 driver files
77include drivers/arm/gic/v2/gicv2.mk
Alexei Fedorovfc4f80e2020-04-07 11:48:00 +010078
Alexei Fedorovcaa18022020-07-14 10:47:25 +010079FVP_GIC_SOURCES := ${GICV2_SOURCES} \
Achin Gupta1fa7eb62015-11-03 14:18:34 +000080 plat/common/plat_gicv2.c \
81 plat/arm/common/arm_gicv2.c
Soby Mathew5f6412a2018-02-08 11:39:38 +000082
83FVP_DT_PREFIX := fvp-base-gicv2-psci
Achin Gupta1fa7eb62015-11-03 14:18:34 +000084else
85$(error "Incorrect GIC driver chosen on FVP port")
86endif
87
Soby Mathew7356b1e2016-03-24 10:12:42 +000088ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI)
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +010089FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c
Soby Mathew7356b1e2016-03-24 10:12:42 +000090else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN)
91FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \
92 plat/arm/common/arm_ccn.c
93else
94$(error "Incorrect CCN driver chosen on FVP port")
95endif
Vikram Kanigirifbb13012016-02-15 11:54:14 +000096
Soby Mathew9c708b52016-02-26 14:23:19 +000097FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000098 plat/arm/board/fvp/fvp_security.c \
99 plat/arm/common/arm_tzc400.c
100
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000101
Juan Castillo31a68f02015-04-14 12:49:03 +0100102PLAT_INCLUDES := -Iplat/arm/board/fvp/include
Sandrine Bailleuxe701e302014-05-20 17:28:25 +0100103
Ryan Harkin25cff832014-01-13 12:37:03 +0000104
Soby Mathewcc037c12016-04-08 16:42:58 +0100105PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c
Ryan Harkin25cff832014-01-13 12:37:03 +0000106
Soby Mathew0d268dc2016-07-11 14:13:56 +0100107FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
108
109ifeq (${ARCH}, aarch64)
John Tsichritzisfe6df392019-03-19 17:20:52 +0000110
John Tsichritzis7557c662019-06-03 13:54:30 +0100111# select a different set of CPU files, depending on whether we compile for
112# hardware assisted coherency cores or not
John Tsichritzisfe6df392019-03-19 17:20:52 +0000113ifeq (${HW_ASSISTED_COHERENCY}, 0)
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100114# Cores used without DSU
John Tsichritzisfe6df392019-03-19 17:20:52 +0000115 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
Soby Mathewc704cbc2014-08-14 11:33:56 +0100116 lib/cpus/aarch64/cortex_a53.S \
117 lib/cpus/aarch64/cortex_a57.S \
Yatharth Kochar63af6872016-02-09 12:00:03 +0000118 lib/cpus/aarch64/cortex_a72.S \
John Tsichritzisfe6df392019-03-19 17:20:52 +0000119 lib/cpus/aarch64/cortex_a73.S
120else
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100121# Cores used with DSU only
John Tsichritzis7557c662019-06-03 13:54:30 +0100122 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100123 # AArch64-only cores
John Tsichritzis7557c662019-06-03 13:54:30 +0100124 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
125 lib/cpus/aarch64/cortex_a76ae.S \
Balint Dobszaycc942642019-07-03 13:02:56 +0200126 lib/cpus/aarch64/cortex_a77.S \
Jimmy Brisson7ec175e2020-06-01 16:49:34 -0500127 lib/cpus/aarch64/cortex_a78.S \
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100128 lib/cpus/aarch64/neoverse_n_common.S \
John Tsichritzis7557c662019-06-03 13:54:30 +0100129 lib/cpus/aarch64/neoverse_n1.S \
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100130 lib/cpus/aarch64/neoverse_n2.S \
John Tsichritzis7557c662019-06-03 13:54:30 +0100131 lib/cpus/aarch64/neoverse_e1.S \
Jimmy Brisson958a0b12020-09-30 15:28:03 -0500132 lib/cpus/aarch64/neoverse_v1.S \
Jimmy Brisson7cc90c42020-09-30 15:34:51 -0500133 lib/cpus/aarch64/cortex_a78_ae.S \
johpow01a3810e82021-05-18 15:23:31 -0500134 lib/cpus/aarch64/cortex_a510.S \
135 lib/cpus/aarch64/cortex_a710.S \
johpow01aef12f22020-10-15 13:40:04 -0500136 lib/cpus/aarch64/cortex_makalu.S \
johpow014c42c0d2021-04-20 17:05:04 -0500137 lib/cpus/aarch64/cortex_makalu_elp_arm.S \
johpow01f0c8b262021-07-07 17:06:07 -0500138 lib/cpus/aarch64/cortex_demeter.S \
Imre Kis584410e2019-07-22 14:36:30 +0200139 lib/cpus/aarch64/cortex_a65.S \
Bipin Ravi4da1b0b2021-03-16 15:20:58 -0500140 lib/cpus/aarch64/cortex_a65ae.S \
johpow01449d5d72021-08-19 16:12:50 -0500141 lib/cpus/aarch64/cortex_a78c.S \
142 lib/cpus/aarch64/cortex_hayes.S
John Tsichritzis7557c662019-06-03 13:54:30 +0100143 endif
John Tsichritzisc0c104a2019-08-13 10:11:41 +0100144 # AArch64/AArch32 cores
145 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
146 lib/cpus/aarch64/cortex_a75.S
John Tsichritzisfe6df392019-03-19 17:20:52 +0000147endif
John Tsichritzis6deaf9c2018-10-08 17:09:43 +0100148
Yatharth Kochara4c219a2016-07-12 15:47:03 +0100149else
150FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
Soby Mathew0d268dc2016-07-11 14:13:56 +0100151endif
Sandrine Bailleuxdd505792016-01-13 09:04:26 +0000152
Alexei Fedorov896799a2019-05-09 12:14:40 +0100153BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \
154 drivers/arm/sp805/sp805.c \
Alexei Fedorov7131d832019-08-16 14:15:59 +0100155 drivers/delay_timer/delay_timer.c \
Aditya Angadi20b48412019-04-16 11:29:14 +0530156 drivers/io/io_semihosting.c \
Dan Handley2b6b5742015-03-19 19:17:53 +0000157 lib/semihosting/semihosting.c \
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100158 lib/semihosting/${ARCH}/semihosting_call.S \
159 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
Dan Handleyd617f662015-04-27 19:17:18 +0100160 plat/arm/board/fvp/fvp_bl1_setup.c \
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100161 plat/arm/board/fvp/fvp_err.c \
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000162 plat/arm/board/fvp/fvp_io_storage.c \
163 ${FVP_CPU_LIBS} \
164 ${FVP_INTERCONNECT_SOURCES}
165
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500166ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov7131d832019-08-16 14:15:59 +0100167BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
168else
169BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c
170endif
171
Ryan Harkin25cff832014-01-13 12:37:03 +0000172
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100173BL2_SOURCES += drivers/arm/sp805/sp805.c \
174 drivers/io/io_semihosting.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100175 lib/utils/mem_region.c \
Dan Handley2b6b5742015-03-19 19:17:53 +0000176 lib/semihosting/semihosting.c \
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100177 lib/semihosting/${ARCH}/semihosting_call.S \
Dan Handleyd617f662015-04-27 19:17:18 +0100178 plat/arm/board/fvp/fvp_bl2_setup.c \
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100179 plat/arm/board/fvp/fvp_err.c \
Dan Handleyd617f662015-04-27 19:17:18 +0100180 plat/arm/board/fvp/fvp_io_storage.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100181 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000182 ${FVP_SECURITY_SOURCES}
Ryan Harkin25cff832014-01-13 12:37:03 +0000183
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100184
Manish V Badarkhe09a192c2020-08-23 09:58:44 +0100185ifeq (${COT_DESC_IN_DTB},1)
186BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c
187endif
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100188
Roberto Vargas52207802017-11-17 13:22:18 +0000189ifeq (${BL2_AT_EL3},1)
190BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
191 plat/arm/board/fvp/fvp_bl2_el3_setup.c \
192 ${FVP_CPU_LIBS} \
193 ${FVP_INTERCONNECT_SOURCES}
194endif
195
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500196ifeq (${USE_SP804_TIMER},1)
Antonio Nino Diaz664adb62016-05-17 09:48:10 +0100197BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
Antonio Nino Diaz664adb62016-05-17 09:48:10 +0100198endif
199
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100200BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000201 ${FVP_SECURITY_SOURCES}
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100202
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500203ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov7131d832019-08-16 14:15:59 +0100204BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
205endif
206
Antonio Nino Diazf13d09a2019-01-23 21:50:09 +0000207BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \
208 drivers/arm/smmu/smmu_v3.c \
Alexei Fedorov7131d832019-08-16 14:15:59 +0100209 drivers/delay_timer/delay_timer.c \
Antonio Nino Diazd7da2f82018-10-10 11:14:44 +0100210 drivers/cfi/v2m/v2m_flash.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100211 lib/utils/mem_region.c \
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100212 plat/arm/board/fvp/fvp_bl31_setup.c \
Madhukar Pappireddyd0cf0a92020-04-16 17:54:25 -0500213 plat/arm/board/fvp/fvp_console.c \
Dan Handleyd617f662015-04-27 19:17:18 +0100214 plat/arm/board/fvp/fvp_pm.c \
Dan Handleyd617f662015-04-27 19:17:18 +0100215 plat/arm/board/fvp/fvp_topology.c \
216 plat/arm/board/fvp/aarch64/fvp_helpers.S \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +0100217 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000218 ${FVP_CPU_LIBS} \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000219 ${FVP_GIC_SOURCES} \
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000220 ${FVP_INTERCONNECT_SOURCES} \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +0000221 ${FVP_SECURITY_SOURCES}
Juan Castillo5e29c752015-01-07 10:39:25 +0000222
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600223# Support for fconf in BL31
224# Added separately from the above list for better readability
Madhukar Pappireddyaa1121f2020-03-13 13:00:17 -0500225ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31}),)
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600226BL31_SOURCES += common/fdt_wrappers.c \
227 lib/fconf/fconf.c \
Manish V Badarkhe8717e032020-05-30 17:40:44 +0100228 lib/fconf/fconf_dyn_cfg_getter.c \
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600229 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
Madhukar Pappireddy02cc3ff2020-06-02 09:26:30 -0500230
231ifeq (${SEC_INT_DESC_IN_FCONF},1)
232BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c
233endif
234
Madhukar Pappireddyaa1121f2020-03-13 13:00:17 -0500235endif
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600236
Madhukar Pappireddy7a554a12020-08-12 13:18:19 -0500237ifeq (${USE_SP804_TIMER},1)
Alexei Fedorov7131d832019-08-16 14:15:59 +0100238BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
239else
240BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c
241endif
242
Soby Mathewa684e582018-02-27 11:17:14 +0000243# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
244ifdef UNIX_MK
Soby Mathew5f6412a2018-02-08 11:39:38 +0000245FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts
Soby Mathewb6814842018-04-04 09:40:32 +0100246FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \
Louis Mayencourt6d2b5732019-12-17 13:17:25 +0000247 ${PLAT}_fw_config.dts \
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100248 ${PLAT}_tb_fw_config.dts \
Soby Mathewb6814842018-04-04 09:40:32 +0100249 ${PLAT}_soc_fw_config.dts \
250 ${PLAT}_nt_fw_config.dts \
251 )
252
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100253FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
254FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
Soby Mathewb6814842018-04-04 09:40:32 +0100255FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb
256FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
257
258ifeq (${SPD},tspd)
259FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts
260FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb
261
262# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100263$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG}))
Soby Mathewb6814842018-04-04 09:40:32 +0100264endif
Soby Mathew5f6412a2018-02-08 11:39:38 +0000265
Achin Guptada6ef0e2019-10-11 14:54:48 +0100266ifeq (${SPD},spmd)
Olivier Deprezbcaa0682020-04-01 21:28:26 +0200267
268ifeq ($(ARM_SPMC_MANIFEST_DTS),)
269ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts
270endif
271
272FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
273FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb
Achin Guptada6ef0e2019-10-11 14:54:48 +0100274
275# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100276$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG}))
Achin Guptada6ef0e2019-10-11 14:54:48 +0100277endif
278
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100279# Add the FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100280$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG}))
Soby Mathew5f6412a2018-02-08 11:39:38 +0000281# Add the TB_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100282$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG}))
Soby Mathewb6814842018-04-04 09:40:32 +0100283# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100284$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG}))
Soby Mathewb6814842018-04-04 09:40:32 +0100285# Add the NT_FW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100286$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG}))
Soby Mathew5f6412a2018-02-08 11:39:38 +0000287
288FDT_SOURCES += ${FVP_HW_CONFIG_DTS}
289$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
290
291# Add the HW_CONFIG to FIP and specify the same to certtool
Anders Dellien3f694742020-08-23 19:32:48 +0100292$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG}))
Soby Mathewa684e582018-02-27 11:17:14 +0000293endif
Soby Mathew5f6412a2018-02-08 11:39:38 +0000294
Dimitris Papastamos12241b92017-11-14 13:27:41 +0000295# Enable Activity Monitor Unit extensions by default
296ENABLE_AMU := 1
297
Dimitris Papastamos756b8dc2018-05-31 14:10:06 +0100298# Enable dynamic mitigation support by default
299DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
300
Manish Pandey2207e932019-11-06 13:17:46 +0000301# Enable reclaiming of BL31 initialisation code for secondary cores
Ambroise Vincentb7a14972019-07-17 11:17:28 +0100302# stacks for FVP. However, don't enable reclaiming for clang.
Soby Mathew7823d9e2018-10-14 08:13:44 +0100303ifneq (${RESET_TO_BL31},1)
Ambroise Vincentb7a14972019-07-17 11:17:28 +0100304ifeq ($(findstring clang,$(notdir $(CC))),)
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100305RECLAIM_INIT_CODE := 1
Soby Mathew7823d9e2018-10-14 08:13:44 +0100306endif
Ambroise Vincentb7a14972019-07-17 11:17:28 +0100307endif
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100308
Dimitris Papastamosd7e2e9e2017-12-11 11:45:35 +0000309ifeq (${ENABLE_AMU},1)
John Tsichritzisfe6df392019-03-19 17:20:52 +0000310BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \
Dimitris Papastamos0b00f8a2018-02-14 10:00:06 +0000311 lib/cpus/aarch64/cpuamu_helpers.S
John Tsichritzisfe6df392019-03-19 17:20:52 +0000312
313ifeq (${HW_ASSISTED_COHERENCY}, 1)
314BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
315 lib/cpus/aarch64/neoverse_n1_pubsub.c
316endif
Dimitris Papastamosd7e2e9e2017-12-11 11:45:35 +0000317endif
318
Jeenu Viswambharana490fe02018-06-08 08:44:36 +0100319ifeq (${RAS_EXTENSION},1)
320BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c
321endif
322
Douglas Raillard306593d2017-02-24 18:14:15 +0000323ifneq (${ENABLE_STACK_PROTECTOR},0)
324PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c
325endif
326
dp-armcdd03cb2017-02-15 11:07:55 +0000327ifeq (${ARCH},aarch32)
328 NEED_BL32 := yes
329endif
330
Antonio Nino Diaz4e6408c2019-01-23 16:23:07 +0000331# Enable the dynamic translation tables library.
332ifeq (${ARCH},aarch32)
333 ifeq (${RESET_TO_SP_MIN},1)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900334 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Antonio Nino Diaz4e6408c2019-01-23 16:23:07 +0000335 endif
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000336else # AArch64
Antonio Nino Diaz4e6408c2019-01-23 16:23:07 +0000337 ifeq (${RESET_TO_BL31},1)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900338 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Antonio Nino Diaz4e6408c2019-01-23 16:23:07 +0000339 endif
Antonio Nino Diaz60ef6752019-02-12 13:32:03 +0000340 ifeq (${SPD},trusty)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900341 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Antonio Nino Diaz60ef6752019-02-12 13:32:03 +0000342 endif
Antonio Nino Diaz4e6408c2019-01-23 16:23:07 +0000343endif
344
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000345ifeq (${ALLOW_RO_XLAT_TABLES}, 1)
346 ifeq (${ARCH},aarch32)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900347 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000348 else # AArch64
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900349 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000350 ifeq (${SPD},tspd)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900351 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000352 endif
353 endif
354endif
355
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100356ifeq (${USE_DEBUGFS},1)
Masahiro Yamada1adc5f52020-04-01 14:28:24 +0900357 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100358endif
359
Soby Mathew3b5156e2017-10-05 12:27:33 +0100360# Add support for platform supplied linker script for BL31 build
361$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
362
Roberto Vargas9f412482018-01-16 10:35:23 +0000363ifneq (${BL2_AT_EL3}, 0)
364 override BL1_SOURCES =
365endif
366
Juan Castillo31a68f02015-04-14 12:49:03 +0100367include plat/arm/board/common/board_common.mk
Dan Handley2b6b5742015-03-19 19:17:53 +0000368include plat/arm/common/arm_common.mk
Soby Mathew45e39e22018-03-26 15:16:46 +0100369
Max Shvetsov06dba292019-12-06 11:50:12 +0000370ifeq (${TRUSTED_BOARD_BOOT}, 1)
371BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
372BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c
Alexei Fedorov61369a22020-07-13 14:59:02 +0100373
374ifeq (${MEASURED_BOOT},1)
375BL2_SOURCES += plat/arm/board/fvp/fvp_measured_boot.c
376endif
377
Soby Mathew45e39e22018-03-26 15:16:46 +0100378# FVP being a development platform, enable capability to disable Authentication
Antonio Nino Diaz05f49572018-09-25 11:37:23 +0100379# dynamically if TRUSTED_BOARD_BOOT is set.
Max Shvetsov06dba292019-12-06 11:50:12 +0000380DYN_DISABLE_AUTH := 1
Soby Mathew45e39e22018-03-26 15:16:46 +0100381endif
Manish V Badarkhe2d49ef32021-08-24 14:42:35 +0100382
383# enable trace buffer control registers access to NS by default
384ENABLE_TRBE_FOR_NS := 1
385
386# enable trace system registers access to NS by default
387ENABLE_SYS_REG_TRACE_FOR_NS := 1
388
389# enable trace filter control registers access to NS by default
390ENABLE_TRF_FOR_NS := 1