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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dimitris Papastamosa65841a2018-01-22 12:58:52 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01008#include <arch_helpers.h>
Dimitris Papastamosa65841a2018-01-22 12:58:52 +00009#include <arm_arch_svc.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010010#include <assert.h>
Soby Mathew96168382014-12-17 14:47:57 +000011#include <debug.h>
12#include <platform.h>
dp-arm3cac7862016-09-19 11:18:44 +010013#include <pmf.h>
14#include <runtime_instr.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000015#include <smccc.h>
Soby Mathew981487a2015-07-13 14:10:57 +010016#include <string.h>
Dan Handley714a0d22014-04-09 13:13:04 +010017#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
19/*******************************************************************************
20 * PSCI frontend api for servicing SMCs. Described in the PSCI spec.
21 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010022int psci_cpu_on(u_register_t target_cpu,
23 uintptr_t entrypoint,
24 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010025
26{
27 int rc;
Soby Mathew8595b872015-01-06 15:36:38 +000028 entry_point_info_t ep;
Achin Gupta4f6ad662013-10-25 09:08:21 +010029
30 /* Determine if the cpu exists of not */
Soby Mathew981487a2015-07-13 14:10:57 +010031 rc = psci_validate_mpidr(target_cpu);
32 if (rc != PSCI_E_SUCCESS)
Soby Mathew74e52a72014-10-02 16:56:51 +010033 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010034
Soby Mathewf1f97a12015-07-15 12:13:26 +010035 /* Validate the entry point and get the entry_point_info */
36 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew8595b872015-01-06 15:36:38 +000037 if (rc != PSCI_E_SUCCESS)
38 return rc;
39
Soby Mathew8595b872015-01-06 15:36:38 +000040 /*
Soby Mathew981487a2015-07-13 14:10:57 +010041 * To turn this cpu on, specify which power
Achin Gupta0959db52013-12-02 17:33:04 +000042 * levels need to be turned on
43 */
Sandrine Bailleux7497bff2016-04-25 09:28:43 +010044 return psci_cpu_on_start(target_cpu, &ep);
Achin Gupta4f6ad662013-10-25 09:08:21 +010045}
46
47unsigned int psci_version(void)
48{
49 return PSCI_MAJOR_VER | PSCI_MINOR_VER;
50}
51
52int psci_cpu_suspend(unsigned int power_state,
Soby Mathew011ca182015-07-29 17:05:03 +010053 uintptr_t entrypoint,
54 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010055{
56 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +010057 unsigned int target_pwrlvl, is_power_down_state;
Soby Mathew8595b872015-01-06 15:36:38 +000058 entry_point_info_t ep;
Soby Mathew981487a2015-07-13 14:10:57 +010059 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
60 plat_local_state_t cpu_pd_state;
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Soby Mathew981487a2015-07-13 14:10:57 +010062 /* Validate the power_state parameter */
63 rc = psci_validate_power_state(power_state, &state_info);
64 if (rc != PSCI_E_SUCCESS) {
65 assert(rc == PSCI_E_INVALID_PARAMS);
66 return rc;
67 }
Vikram Kanigirif100f412014-04-01 19:26:26 +010068
Soby Mathew981487a2015-07-13 14:10:57 +010069 /*
70 * Get the value of the state type bit from the power state parameter.
71 */
72 is_power_down_state = psci_get_pstate_type(power_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +010073
Soby Mathew981487a2015-07-13 14:10:57 +010074 /* Sanity check the requested suspend levels */
Soby Mathew24ab34f2016-05-03 17:11:42 +010075 assert(psci_validate_suspend_req(&state_info, is_power_down_state)
Soby Mathew981487a2015-07-13 14:10:57 +010076 == PSCI_E_SUCCESS);
Soby Mathew74e52a72014-10-02 16:56:51 +010077
Soby Mathew981487a2015-07-13 14:10:57 +010078 target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
Sandrine Bailleuxf9f3bbf2016-06-22 16:35:01 +010079 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) {
80 ERROR("Invalid target power level for suspend operation\n");
81 panic();
82 }
Soby Mathew981487a2015-07-13 14:10:57 +010083
84 /* Fast path for CPU standby.*/
85 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
86 if (!psci_plat_pm_ops->cpu_standby)
Soby Mathew74e52a72014-10-02 16:56:51 +010087 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010088
Soby Mathew981487a2015-07-13 14:10:57 +010089 /*
90 * Set the state of the CPU power domain to the platform
91 * specific retention state and enter the standby state.
92 */
93 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
94 psci_set_cpu_local_state(cpu_pd_state);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010095
96#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +000097 plat_psci_stat_accounting_start(&state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010098#endif
99
dp-arm3cac7862016-09-19 11:18:44 +0100100#if ENABLE_RUNTIME_INSTRUMENTATION
101 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
102 RT_INSTR_ENTER_HW_LOW_PWR,
103 PMF_NO_CACHE_MAINT);
104#endif
105
Soby Mathew981487a2015-07-13 14:10:57 +0100106 psci_plat_pm_ops->cpu_standby(cpu_pd_state);
Achin Gupta42c52802014-05-09 19:32:25 +0100107
Soby Mathew981487a2015-07-13 14:10:57 +0100108 /* Upon exit from standby, set the state back to RUN. */
109 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Achin Gupta42c52802014-05-09 19:32:25 +0100110
dp-arm3cac7862016-09-19 11:18:44 +0100111#if ENABLE_RUNTIME_INSTRUMENTATION
112 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
113 RT_INSTR_EXIT_HW_LOW_PWR,
114 PMF_NO_CACHE_MAINT);
115#endif
116
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100117#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +0000118 plat_psci_stat_accounting_stop(&state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100119
120 /* Update PSCI stats */
dp-arm66abfbe2017-01-31 13:01:04 +0000121 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100122#endif
123
Soby Mathew74e52a72014-10-02 16:56:51 +0100124 return PSCI_E_SUCCESS;
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000125 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100126
Achin Gupta42c52802014-05-09 19:32:25 +0100127 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100128 * If a power down state has been requested, we need to verify entry
129 * point and program entry information.
Soby Mathew8595b872015-01-06 15:36:38 +0000130 */
Soby Mathew981487a2015-07-13 14:10:57 +0100131 if (is_power_down_state) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100132 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew981487a2015-07-13 14:10:57 +0100133 if (rc != PSCI_E_SUCCESS)
134 return rc;
135 }
Soby Mathewf5121572014-09-30 11:19:51 +0100136
Soby Mathew8595b872015-01-06 15:36:38 +0000137 /*
Achin Gupta42c52802014-05-09 19:32:25 +0100138 * Do what is needed to enter the power down state. Upon success,
Soby Mathew981487a2015-07-13 14:10:57 +0100139 * enter the final wfi which will power down this CPU. This function
140 * might return if the power down was abandoned for any reason, e.g.
141 * arrival of an interrupt
Achin Gupta42c52802014-05-09 19:32:25 +0100142 */
Soby Mathew981487a2015-07-13 14:10:57 +0100143 psci_cpu_suspend_start(&ep,
144 target_pwrlvl,
145 &state_info,
146 is_power_down_state);
Soby Mathew74e52a72014-10-02 16:56:51 +0100147
Soby Mathew74e52a72014-10-02 16:56:51 +0100148 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100149}
150
Soby Mathew011ca182015-07-29 17:05:03 +0100151
152int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
Soby Mathew96168382014-12-17 14:47:57 +0000153{
154 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +0100155 psci_power_state_t state_info;
Soby Mathew96168382014-12-17 14:47:57 +0000156 entry_point_info_t ep;
157
Soby Mathew96168382014-12-17 14:47:57 +0000158 /* Check if the current CPU is the last ON CPU in the system */
159 if (!psci_is_last_on_cpu())
160 return PSCI_E_DENIED;
161
Soby Mathewf1f97a12015-07-15 12:13:26 +0100162 /* Validate the entry point and get the entry_point_info */
163 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew96168382014-12-17 14:47:57 +0000164 if (rc != PSCI_E_SUCCESS)
165 return rc;
166
Soby Mathew981487a2015-07-13 14:10:57 +0100167 /* Query the psci_power_state for system suspend */
168 psci_query_sys_suspend_pwrstate(&state_info);
Soby Mathew96168382014-12-17 14:47:57 +0000169
Soby Mathew981487a2015-07-13 14:10:57 +0100170 /* Ensure that the psci_power_state makes sense */
171 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL);
172 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
173 == PSCI_E_SUCCESS);
174 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]));
Soby Mathew96168382014-12-17 14:47:57 +0000175
176 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100177 * Do what is needed to enter the system suspend state. This function
178 * might return if the power down was abandoned for any reason, e.g.
179 * arrival of an interrupt
Soby Mathew96168382014-12-17 14:47:57 +0000180 */
Soby Mathew981487a2015-07-13 14:10:57 +0100181 psci_cpu_suspend_start(&ep,
182 PLAT_MAX_PWR_LVL,
183 &state_info,
184 PSTATE_TYPE_POWERDOWN);
Soby Mathew96168382014-12-17 14:47:57 +0000185
Soby Mathew96168382014-12-17 14:47:57 +0000186 return PSCI_E_SUCCESS;
187}
188
Achin Gupta4f6ad662013-10-25 09:08:21 +0100189int psci_cpu_off(void)
190{
191 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100192 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100193
Achin Gupta4f6ad662013-10-25 09:08:21 +0100194 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100195 * Do what is needed to power off this CPU and possible higher power
196 * levels if it able to do so. Upon success, enter the final wfi
197 * which will power down this CPU.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100198 */
Soby Mathew981487a2015-07-13 14:10:57 +0100199 rc = psci_do_cpu_off(target_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200
Achin Gupta3140a9e2013-12-02 16:23:12 +0000201 /*
202 * The only error cpu_off can return is E_DENIED. So check if that's
203 * indeed the case.
204 */
Soby Mathew24ab34f2016-05-03 17:11:42 +0100205 assert(rc == PSCI_E_DENIED);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100206
207 return rc;
208}
209
Soby Mathew011ca182015-07-29 17:05:03 +0100210int psci_affinity_info(u_register_t target_affinity,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211 unsigned int lowest_affinity_level)
212{
Varun Wadekar66231d12017-06-07 09:57:42 -0700213 int target_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100214
Soby Mathew981487a2015-07-13 14:10:57 +0100215 /* We dont support level higher than PSCI_CPU_PWR_LVL */
216 if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
217 return PSCI_E_INVALID_PARAMS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100218
Soby Mathew981487a2015-07-13 14:10:57 +0100219 /* Calculate the cpu index of the target */
220 target_idx = plat_core_pos_by_mpidr(target_affinity);
221 if (target_idx == -1)
222 return PSCI_E_INVALID_PARAMS;
Achin Gupta75f73672013-12-05 16:33:10 +0000223
Roberto Vargas6dc82142017-11-13 08:24:07 +0000224 /*
225 * Generic management:
226 * Perform cache maintanence ahead of reading the target CPU state to
227 * ensure that the data is not stale.
228 * There is a theoretical edge case where the cache may contain stale
229 * data for the target CPU data - this can occur under the following
230 * conditions:
231 * - the target CPU is in another cluster from the current
232 * - the target CPU was the last CPU to shutdown on its cluster
233 * - the cluster was removed from coherency as part of the CPU shutdown
234 *
235 * In this case the cache maintenace that was performed as part of the
236 * target CPUs shutdown was not seen by the current CPU's cluster. And
237 * so the cache may contain stale data for the target CPU.
238 */
239 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state);
240
Soby Mathew981487a2015-07-13 14:10:57 +0100241 return psci_get_aff_info_state_by_idx(target_idx);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242}
243
Soby Mathew011ca182015-07-29 17:05:03 +0100244int psci_migrate(u_register_t target_cpu)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100245{
Soby Mathew110fe362014-10-23 10:35:34 +0100246 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100247 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100248
249 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
250 if (rc != PSCI_TOS_UP_MIG_CAP)
251 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
252 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
253
254 /*
255 * Migrate should only be invoked on the CPU where
256 * the Secure OS is resident.
257 */
258 if (resident_cpu_mpidr != read_mpidr_el1())
259 return PSCI_E_NOT_PRESENT;
260
261 /* Check the validity of the specified target cpu */
Soby Mathew981487a2015-07-13 14:10:57 +0100262 rc = psci_validate_mpidr(target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100263 if (rc != PSCI_E_SUCCESS)
264 return PSCI_E_INVALID_PARAMS;
265
266 assert(psci_spd_pm && psci_spd_pm->svc_migrate);
267
268 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
269 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
270
271 return rc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100272}
273
Soby Mathew110fe362014-10-23 10:35:34 +0100274int psci_migrate_info_type(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100275{
Soby Mathew011ca182015-07-29 17:05:03 +0100276 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100277
278 return psci_spd_migrate_info(&resident_cpu_mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100279}
280
Soby Mathew110fe362014-10-23 10:35:34 +0100281long psci_migrate_info_up_cpu(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100282{
Soby Mathew011ca182015-07-29 17:05:03 +0100283 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100284 int rc;
285
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286 /*
Soby Mathew110fe362014-10-23 10:35:34 +0100287 * Return value of this depends upon what
288 * psci_spd_migrate_info() returns.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100289 */
Soby Mathew110fe362014-10-23 10:35:34 +0100290 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
291 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP)
292 return PSCI_E_INVALID_PARAMS;
293
294 return resident_cpu_mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100295}
296
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100297int psci_node_hw_state(u_register_t target_cpu,
298 unsigned int power_level)
299{
300 int rc;
301
302 /* Validate target_cpu */
303 rc = psci_validate_mpidr(target_cpu);
304 if (rc != PSCI_E_SUCCESS)
305 return PSCI_E_INVALID_PARAMS;
306
307 /* Validate power_level against PLAT_MAX_PWR_LVL */
308 if (power_level > PLAT_MAX_PWR_LVL)
309 return PSCI_E_INVALID_PARAMS;
310
311 /*
312 * Dispatch this call to platform to query power controller, and pass on
313 * to the caller what it returns
314 */
315 assert(psci_plat_pm_ops->get_node_hw_state);
316 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level);
317 assert((rc >= HW_ON && rc <= HW_STANDBY) || rc == PSCI_E_NOT_SUPPORTED
318 || rc == PSCI_E_INVALID_PARAMS);
319 return rc;
320}
321
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000322int psci_features(unsigned int psci_fid)
323{
Soby Mathew011ca182015-07-29 17:05:03 +0100324 unsigned int local_caps = psci_caps;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000325
Dimitris Papastamosa65841a2018-01-22 12:58:52 +0000326 if (psci_fid == SMCCC_VERSION)
327 return PSCI_E_SUCCESS;
328
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000329 /* Check if it is a 64 bit function */
330 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
331 local_caps &= PSCI_CAP_64BIT_MASK;
332
333 /* Check for invalid fid */
334 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
335 && is_psci_fid(psci_fid)))
336 return PSCI_E_NOT_SUPPORTED;
337
338
339 /* Check if the psci fid is supported or not */
340 if (!(local_caps & define_psci_cap(psci_fid)))
341 return PSCI_E_NOT_SUPPORTED;
342
343 /* Format the feature flags */
344 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 ||
345 psci_fid == PSCI_CPU_SUSPEND_AARCH64) {
346 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100347 * The trusted firmware does not support OS Initiated Mode.
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000348 */
Soby Mathew981487a2015-07-13 14:10:57 +0100349 return (FF_PSTATE << FF_PSTATE_SHIFT) |
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000350 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT);
351 }
352
353 /* Return 0 for all other fid's */
354 return PSCI_E_SUCCESS;
355}
356
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000357/*******************************************************************************
358 * PSCI top level handler for servicing SMCs.
359 ******************************************************************************/
Soby Mathewd0194872016-04-29 19:01:30 +0100360u_register_t psci_smc_handler(uint32_t smc_fid,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100361 u_register_t x1,
362 u_register_t x2,
363 u_register_t x3,
364 u_register_t x4,
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000365 void *cookie,
366 void *handle,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100367 u_register_t flags)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000368{
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100369 if (is_caller_secure(flags))
Soby Mathewd0194872016-04-29 19:01:30 +0100370 return SMC_UNK;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000371
Soby Mathew61e615b2015-01-15 11:49:49 +0000372 /* Check the fid against the capabilities */
373 if (!(psci_caps & define_psci_cap(smc_fid)))
Soby Mathewd0194872016-04-29 19:01:30 +0100374 return SMC_UNK;
Soby Mathew61e615b2015-01-15 11:49:49 +0000375
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100376 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
377 /* 32-bit PSCI function, clear top parameter bits */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000378
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100379 x1 = (uint32_t)x1;
380 x2 = (uint32_t)x2;
381 x3 = (uint32_t)x3;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000382
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100383 switch (smc_fid) {
384 case PSCI_VERSION:
Soby Mathewd0194872016-04-29 19:01:30 +0100385 return psci_version();
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000386
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100387 case PSCI_CPU_OFF:
Soby Mathewd0194872016-04-29 19:01:30 +0100388 return psci_cpu_off();
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000389
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100390 case PSCI_CPU_SUSPEND_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100391 return psci_cpu_suspend(x1, x2, x3);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000392
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100393 case PSCI_CPU_ON_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100394 return psci_cpu_on(x1, x2, x3);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000395
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100396 case PSCI_AFFINITY_INFO_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100397 return psci_affinity_info(x1, x2);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000398
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100399 case PSCI_MIG_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100400 return psci_migrate(x1);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000401
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100402 case PSCI_MIG_INFO_TYPE:
Soby Mathewd0194872016-04-29 19:01:30 +0100403 return psci_migrate_info_type();
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100404
405 case PSCI_MIG_INFO_UP_CPU_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100406 return psci_migrate_info_up_cpu();
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100407
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100408 case PSCI_NODE_HW_STATE_AARCH32:
409 return psci_node_hw_state(x1, x2);
410
Soby Mathew96168382014-12-17 14:47:57 +0000411 case PSCI_SYSTEM_SUSPEND_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100412 return psci_system_suspend(x1, x2);
Soby Mathew96168382014-12-17 14:47:57 +0000413
Juan Castillo4dc4a472014-08-12 11:17:06 +0100414 case PSCI_SYSTEM_OFF:
415 psci_system_off();
416 /* We should never return from psci_system_off() */
Jonathan Wrightde701832018-03-13 17:45:42 +0000417 break;
Juan Castillo4dc4a472014-08-12 11:17:06 +0100418
419 case PSCI_SYSTEM_RESET:
420 psci_system_reset();
421 /* We should never return from psci_system_reset() */
Jonathan Wrightde701832018-03-13 17:45:42 +0000422 break;
Juan Castillo4dc4a472014-08-12 11:17:06 +0100423
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000424 case PSCI_FEATURES:
Soby Mathewd0194872016-04-29 19:01:30 +0100425 return psci_features(x1);
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000426
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100427#if ENABLE_PSCI_STAT
428 case PSCI_STAT_RESIDENCY_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100429 return psci_stat_residency(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100430
431 case PSCI_STAT_COUNT_AARCH32:
Soby Mathewd0194872016-04-29 19:01:30 +0100432 return psci_stat_count(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100433#endif
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100434 case PSCI_MEM_PROTECT:
435 return psci_mem_protect(x1);
436
437 case PSCI_MEM_CHK_RANGE_AARCH32:
438 return psci_mem_chk_range(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100439
Roberto Vargasb820ad02017-07-26 09:23:09 +0100440 case PSCI_SYSTEM_RESET2_AARCH32:
441 /* We should never return from psci_system_reset2() */
442 return psci_system_reset2(x1, x2);
443
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100444 default:
445 break;
446 }
447 } else {
448 /* 64-bit PSCI function */
449
450 switch (smc_fid) {
451 case PSCI_CPU_SUSPEND_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100452 return psci_cpu_suspend(x1, x2, x3);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100453
454 case PSCI_CPU_ON_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100455 return psci_cpu_on(x1, x2, x3);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100456
457 case PSCI_AFFINITY_INFO_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100458 return psci_affinity_info(x1, x2);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100459
460 case PSCI_MIG_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100461 return psci_migrate(x1);
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100462
463 case PSCI_MIG_INFO_UP_CPU_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100464 return psci_migrate_info_up_cpu();
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100465
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100466 case PSCI_NODE_HW_STATE_AARCH64:
467 return psci_node_hw_state(x1, x2);
468
Soby Mathew96168382014-12-17 14:47:57 +0000469 case PSCI_SYSTEM_SUSPEND_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100470 return psci_system_suspend(x1, x2);
Soby Mathew96168382014-12-17 14:47:57 +0000471
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100472#if ENABLE_PSCI_STAT
473 case PSCI_STAT_RESIDENCY_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100474 return psci_stat_residency(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100475
476 case PSCI_STAT_COUNT_AARCH64:
Soby Mathewd0194872016-04-29 19:01:30 +0100477 return psci_stat_count(x1, x2);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100478#endif
479
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100480 case PSCI_MEM_CHK_RANGE_AARCH64:
481 return psci_mem_chk_range(x1, x2);
482
Roberto Vargasb820ad02017-07-26 09:23:09 +0100483 case PSCI_SYSTEM_RESET2_AARCH64:
484 /* We should never return from psci_system_reset2() */
485 return psci_system_reset2(x1, x2);
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100486
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100487 default:
488 break;
489 }
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000490 }
491
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100492 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid);
Soby Mathewd0194872016-04-29 19:01:30 +0100493 return SMC_UNK;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000494}