Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 6 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 7 | #include <asm_macros.S> |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 8 | #include <assert_macros.S> |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 9 | #include <bl_common.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 10 | #include <cortex_a57.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 11 | #include <cpu_macros.S> |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 12 | #include <debug.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 13 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 14 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 15 | /* --------------------------------------------- |
| 16 | * Disable L1 data cache and unified L2 cache |
| 17 | * --------------------------------------------- |
| 18 | */ |
| 19 | func cortex_a57_disable_dcache |
| 20 | mrs x1, sctlr_el3 |
| 21 | bic x1, x1, #SCTLR_C_BIT |
| 22 | msr sctlr_el3, x1 |
| 23 | isb |
| 24 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 25 | endfunc cortex_a57_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 26 | |
| 27 | /* --------------------------------------------- |
| 28 | * Disable all types of L2 prefetches. |
| 29 | * --------------------------------------------- |
| 30 | */ |
| 31 | func cortex_a57_disable_l2_prefetch |
| 32 | mrs x0, CPUECTLR_EL1 |
| 33 | orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 34 | mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK |
| 35 | orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK |
| 36 | bic x0, x0, x1 |
| 37 | msr CPUECTLR_EL1, x0 |
| 38 | isb |
Soby Mathew | 1604fa0 | 2014-09-22 12:15:26 +0100 | [diff] [blame] | 39 | dsb ish |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 40 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 41 | endfunc cortex_a57_disable_l2_prefetch |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 42 | |
| 43 | /* --------------------------------------------- |
| 44 | * Disable intra-cluster coherency |
| 45 | * --------------------------------------------- |
| 46 | */ |
| 47 | func cortex_a57_disable_smp |
| 48 | mrs x0, CPUECTLR_EL1 |
| 49 | bic x0, x0, #CPUECTLR_SMP_BIT |
| 50 | msr CPUECTLR_EL1, x0 |
| 51 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 52 | endfunc cortex_a57_disable_smp |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 53 | |
| 54 | /* --------------------------------------------- |
| 55 | * Disable debug interfaces |
| 56 | * --------------------------------------------- |
| 57 | */ |
| 58 | func cortex_a57_disable_ext_debug |
| 59 | mov x0, #1 |
| 60 | msr osdlr_el1, x0 |
| 61 | isb |
| 62 | dsb sy |
| 63 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 64 | endfunc cortex_a57_disable_ext_debug |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 65 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 66 | /* -------------------------------------------------- |
| 67 | * Errata Workaround for Cortex A57 Errata #806969. |
| 68 | * This applies only to revision r0p0 of Cortex A57. |
| 69 | * Inputs: |
| 70 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 71 | * Shall clobber: x0-x17 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 72 | * -------------------------------------------------- |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 73 | */ |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 74 | func errata_a57_806969_wa |
| 75 | /* |
| 76 | * Compare x0 against revision r0p0 |
| 77 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 78 | mov x17, x30 |
| 79 | bl check_errata_806969 |
| 80 | cbz x0, 1f |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 81 | mrs x1, CPUACTLR_EL1 |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 82 | orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 83 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 84 | 1: |
| 85 | ret x17 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 86 | endfunc errata_a57_806969_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 87 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 88 | func check_errata_806969 |
| 89 | mov x1, #0x00 |
| 90 | b cpu_rev_var_ls |
| 91 | endfunc check_errata_806969 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 92 | |
| 93 | /* --------------------------------------------------- |
Antonio Nino Diaz | 3f13c35 | 2017-02-24 11:39:22 +0000 | [diff] [blame] | 94 | * Errata Workaround for Cortex A57 Errata #813419. |
| 95 | * This applies only to revision r0p0 of Cortex A57. |
| 96 | * --------------------------------------------------- |
| 97 | */ |
| 98 | func check_errata_813419 |
| 99 | /* |
| 100 | * Even though this is only needed for revision r0p0, it |
| 101 | * is always applied due to limitations of the current |
| 102 | * errata framework. |
| 103 | */ |
| 104 | mov x0, #ERRATA_APPLIES |
| 105 | ret |
| 106 | endfunc check_errata_813419 |
| 107 | |
| 108 | /* --------------------------------------------------- |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 109 | * Errata Workaround for Cortex A57 Errata #813420. |
| 110 | * This applies only to revision r0p0 of Cortex A57. |
| 111 | * Inputs: |
| 112 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 113 | * Shall clobber: x0-x17 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 114 | * --------------------------------------------------- |
| 115 | */ |
| 116 | func errata_a57_813420_wa |
| 117 | /* |
| 118 | * Compare x0 against revision r0p0 |
| 119 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 120 | mov x17, x30 |
| 121 | bl check_errata_813420 |
| 122 | cbz x0, 1f |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 123 | mrs x1, CPUACTLR_EL1 |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 124 | orr x1, x1, #CPUACTLR_DCC_AS_DCCI |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 125 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 126 | 1: |
| 127 | ret x17 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 128 | endfunc errata_a57_813420_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 129 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 130 | func check_errata_813420 |
| 131 | mov x1, #0x00 |
| 132 | b cpu_rev_var_ls |
| 133 | endfunc check_errata_813420 |
| 134 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 135 | /* -------------------------------------------------------------------- |
| 136 | * Disable the over-read from the LDNP instruction. |
| 137 | * |
| 138 | * This applies to all revisions <= r1p2. The performance degradation |
| 139 | * observed with LDNP/STNP has been fixed on r1p3 and onwards. |
| 140 | * |
| 141 | * Inputs: |
| 142 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 143 | * Shall clobber: x0-x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 144 | * --------------------------------------------------------------------- |
| 145 | */ |
| 146 | func a57_disable_ldnp_overread |
| 147 | /* |
| 148 | * Compare x0 against revision r1p2 |
| 149 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 150 | mov x17, x30 |
| 151 | bl check_errata_disable_ldnp_overread |
| 152 | cbz x0, 1f |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 153 | mrs x1, CPUACTLR_EL1 |
| 154 | orr x1, x1, #CPUACTLR_DIS_OVERREAD |
| 155 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 156 | 1: |
| 157 | ret x17 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 158 | endfunc a57_disable_ldnp_overread |
| 159 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 160 | func check_errata_disable_ldnp_overread |
| 161 | mov x1, #0x12 |
| 162 | b cpu_rev_var_ls |
| 163 | endfunc check_errata_disable_ldnp_overread |
| 164 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 165 | /* --------------------------------------------------- |
| 166 | * Errata Workaround for Cortex A57 Errata #826974. |
| 167 | * This applies only to revision <= r1p1 of Cortex A57. |
| 168 | * Inputs: |
| 169 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 170 | * Shall clobber: x0-x17 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 171 | * --------------------------------------------------- |
| 172 | */ |
| 173 | func errata_a57_826974_wa |
| 174 | /* |
| 175 | * Compare x0 against revision r1p1 |
| 176 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 177 | mov x17, x30 |
| 178 | bl check_errata_826974 |
| 179 | cbz x0, 1f |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 180 | mrs x1, CPUACTLR_EL1 |
| 181 | orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB |
| 182 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 183 | 1: |
| 184 | ret x17 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 185 | endfunc errata_a57_826974_wa |
| 186 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 187 | func check_errata_826974 |
| 188 | mov x1, #0x11 |
| 189 | b cpu_rev_var_ls |
| 190 | endfunc check_errata_826974 |
| 191 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 192 | /* --------------------------------------------------- |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 193 | * Errata Workaround for Cortex A57 Errata #826977. |
| 194 | * This applies only to revision <= r1p1 of Cortex A57. |
| 195 | * Inputs: |
| 196 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 197 | * Shall clobber: x0-x17 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 198 | * --------------------------------------------------- |
| 199 | */ |
| 200 | func errata_a57_826977_wa |
| 201 | /* |
| 202 | * Compare x0 against revision r1p1 |
| 203 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 204 | mov x17, x30 |
| 205 | bl check_errata_826977 |
| 206 | cbz x0, 1f |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 207 | mrs x1, CPUACTLR_EL1 |
| 208 | orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE |
| 209 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 210 | 1: |
| 211 | ret x17 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 212 | endfunc errata_a57_826977_wa |
| 213 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 214 | func check_errata_826977 |
| 215 | mov x1, #0x11 |
| 216 | b cpu_rev_var_ls |
| 217 | endfunc check_errata_826977 |
| 218 | |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 219 | /* --------------------------------------------------- |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 220 | * Errata Workaround for Cortex A57 Errata #828024. |
| 221 | * This applies only to revision <= r1p1 of Cortex A57. |
| 222 | * Inputs: |
| 223 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 224 | * Shall clobber: x0-x17 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 225 | * --------------------------------------------------- |
| 226 | */ |
| 227 | func errata_a57_828024_wa |
| 228 | /* |
| 229 | * Compare x0 against revision r1p1 |
| 230 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 231 | mov x17, x30 |
| 232 | bl check_errata_828024 |
| 233 | cbz x0, 1f |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 234 | mrs x1, CPUACTLR_EL1 |
| 235 | /* |
| 236 | * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 |
| 237 | * instructions here because the resulting bitmask doesn't fit in a |
| 238 | * 16-bit value so it cannot be encoded in a single instruction. |
| 239 | */ |
| 240 | orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA |
| 241 | orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) |
| 242 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 243 | 1: |
| 244 | ret x17 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 245 | endfunc errata_a57_828024_wa |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 246 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 247 | func check_errata_828024 |
| 248 | mov x1, #0x11 |
| 249 | b cpu_rev_var_ls |
| 250 | endfunc check_errata_828024 |
| 251 | |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 252 | /* --------------------------------------------------- |
| 253 | * Errata Workaround for Cortex A57 Errata #829520. |
| 254 | * This applies only to revision <= r1p2 of Cortex A57. |
| 255 | * Inputs: |
| 256 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 257 | * Shall clobber: x0-x17 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 258 | * --------------------------------------------------- |
| 259 | */ |
| 260 | func errata_a57_829520_wa |
| 261 | /* |
| 262 | * Compare x0 against revision r1p2 |
| 263 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 264 | mov x17, x30 |
| 265 | bl check_errata_829520 |
| 266 | cbz x0, 1f |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 267 | mrs x1, CPUACTLR_EL1 |
| 268 | orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR |
| 269 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 270 | 1: |
| 271 | ret x17 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 272 | endfunc errata_a57_829520_wa |
| 273 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 274 | func check_errata_829520 |
| 275 | mov x1, #0x12 |
| 276 | b cpu_rev_var_ls |
| 277 | endfunc check_errata_829520 |
| 278 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 279 | /* --------------------------------------------------- |
| 280 | * Errata Workaround for Cortex A57 Errata #833471. |
| 281 | * This applies only to revision <= r1p2 of Cortex A57. |
| 282 | * Inputs: |
| 283 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 284 | * Shall clobber: x0-x17 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 285 | * --------------------------------------------------- |
| 286 | */ |
| 287 | func errata_a57_833471_wa |
| 288 | /* |
| 289 | * Compare x0 against revision r1p2 |
| 290 | */ |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 291 | mov x17, x30 |
| 292 | bl check_errata_833471 |
| 293 | cbz x0, 1f |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 294 | mrs x1, CPUACTLR_EL1 |
| 295 | orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH |
| 296 | msr CPUACTLR_EL1, x1 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 297 | 1: |
| 298 | ret x17 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 299 | endfunc errata_a57_833471_wa |
| 300 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 301 | func check_errata_833471 |
| 302 | mov x1, #0x12 |
| 303 | b cpu_rev_var_ls |
| 304 | endfunc check_errata_833471 |
| 305 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 306 | /* ------------------------------------------------- |
| 307 | * The CPU Ops reset function for Cortex-A57. |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 308 | * Shall clobber: x0-x19 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 309 | * ------------------------------------------------- |
| 310 | */ |
| 311 | func cortex_a57_reset_func |
| 312 | mov x19, x30 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 313 | bl cpu_get_rev_var |
| 314 | mov x18, x0 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 315 | |
| 316 | #if ERRATA_A57_806969 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 317 | mov x0, x18 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 318 | bl errata_a57_806969_wa |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 319 | #endif |
| 320 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 321 | #if ERRATA_A57_813420 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 322 | mov x0, x18 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 323 | bl errata_a57_813420_wa |
| 324 | #endif |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 325 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 326 | #if A57_DISABLE_NON_TEMPORAL_HINT |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 327 | mov x0, x18 |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 328 | bl a57_disable_ldnp_overread |
| 329 | #endif |
| 330 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 331 | #if ERRATA_A57_826974 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 332 | mov x0, x18 |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 333 | bl errata_a57_826974_wa |
| 334 | #endif |
| 335 | |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 336 | #if ERRATA_A57_826977 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 337 | mov x0, x18 |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 338 | bl errata_a57_826977_wa |
| 339 | #endif |
| 340 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 341 | #if ERRATA_A57_828024 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 342 | mov x0, x18 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 343 | bl errata_a57_828024_wa |
| 344 | #endif |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 345 | |
| 346 | #if ERRATA_A57_829520 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 347 | mov x0, x18 |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 348 | bl errata_a57_829520_wa |
| 349 | #endif |
| 350 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 351 | #if ERRATA_A57_833471 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 352 | mov x0, x18 |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 353 | bl errata_a57_833471_wa |
| 354 | #endif |
| 355 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 356 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 357 | * Enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 358 | * --------------------------------------------- |
| 359 | */ |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 360 | mrs x0, CPUECTLR_EL1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 361 | orr x0, x0, #CPUECTLR_SMP_BIT |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 362 | msr CPUECTLR_EL1, x0 |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 363 | isb |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 364 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 365 | endfunc cortex_a57_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 366 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 367 | /* ---------------------------------------------------- |
| 368 | * The CPU Ops core power down function for Cortex-A57. |
| 369 | * ---------------------------------------------------- |
| 370 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 371 | func cortex_a57_core_pwr_dwn |
| 372 | mov x18, x30 |
| 373 | |
| 374 | /* --------------------------------------------- |
| 375 | * Turn off caches. |
| 376 | * --------------------------------------------- |
| 377 | */ |
| 378 | bl cortex_a57_disable_dcache |
| 379 | |
| 380 | /* --------------------------------------------- |
| 381 | * Disable the L2 prefetches. |
| 382 | * --------------------------------------------- |
| 383 | */ |
| 384 | bl cortex_a57_disable_l2_prefetch |
| 385 | |
| 386 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 387 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 388 | * --------------------------------------------- |
| 389 | */ |
| 390 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 391 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 392 | |
| 393 | /* --------------------------------------------- |
| 394 | * Come out of intra cluster coherency |
| 395 | * --------------------------------------------- |
| 396 | */ |
| 397 | bl cortex_a57_disable_smp |
| 398 | |
| 399 | /* --------------------------------------------- |
| 400 | * Force the debug interfaces to be quiescent |
| 401 | * --------------------------------------------- |
| 402 | */ |
| 403 | mov x30, x18 |
| 404 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 405 | endfunc cortex_a57_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 406 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 407 | /* ------------------------------------------------------- |
| 408 | * The CPU Ops cluster power down function for Cortex-A57. |
| 409 | * ------------------------------------------------------- |
| 410 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 411 | func cortex_a57_cluster_pwr_dwn |
| 412 | mov x18, x30 |
| 413 | |
| 414 | /* --------------------------------------------- |
| 415 | * Turn off caches. |
| 416 | * --------------------------------------------- |
| 417 | */ |
| 418 | bl cortex_a57_disable_dcache |
| 419 | |
| 420 | /* --------------------------------------------- |
| 421 | * Disable the L2 prefetches. |
| 422 | * --------------------------------------------- |
| 423 | */ |
| 424 | bl cortex_a57_disable_l2_prefetch |
| 425 | |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 426 | #if !SKIP_A57_L1_FLUSH_PWR_DWN |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 427 | /* ------------------------------------------------- |
| 428 | * Flush the L1 caches. |
| 429 | * ------------------------------------------------- |
| 430 | */ |
| 431 | mov x0, #DCCISW |
| 432 | bl dcsw_op_level1 |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 433 | #endif |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 434 | /* --------------------------------------------- |
| 435 | * Disable the optional ACP. |
| 436 | * --------------------------------------------- |
| 437 | */ |
| 438 | bl plat_disable_acp |
| 439 | |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 440 | /* ------------------------------------------------- |
| 441 | * Flush the L2 caches. |
| 442 | * ------------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 443 | */ |
| 444 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 445 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 446 | |
| 447 | /* --------------------------------------------- |
| 448 | * Come out of intra cluster coherency |
| 449 | * --------------------------------------------- |
| 450 | */ |
| 451 | bl cortex_a57_disable_smp |
| 452 | |
| 453 | /* --------------------------------------------- |
| 454 | * Force the debug interfaces to be quiescent |
| 455 | * --------------------------------------------- |
| 456 | */ |
| 457 | mov x30, x18 |
| 458 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 459 | endfunc cortex_a57_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 460 | |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 461 | #if REPORT_ERRATA |
| 462 | /* |
| 463 | * Errata printing function for Cortex A57. Must follow AAPCS. |
| 464 | */ |
| 465 | func cortex_a57_errata_report |
| 466 | stp x8, x30, [sp, #-16]! |
| 467 | |
| 468 | bl cpu_get_rev_var |
| 469 | mov x8, x0 |
| 470 | |
| 471 | /* |
| 472 | * Report all errata. The revision-variant information is passed to |
| 473 | * checking functions of each errata. |
| 474 | */ |
| 475 | report_errata ERRATA_A57_806969, cortex_a57, 806969 |
Antonio Nino Diaz | 3f13c35 | 2017-02-24 11:39:22 +0000 | [diff] [blame] | 476 | report_errata ERRATA_A57_813419, cortex_a57, 813419 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 477 | report_errata ERRATA_A57_813420, cortex_a57, 813420 |
| 478 | report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ |
| 479 | disable_ldnp_overread |
| 480 | report_errata ERRATA_A57_826974, cortex_a57, 826974 |
| 481 | report_errata ERRATA_A57_826977, cortex_a57, 826977 |
| 482 | report_errata ERRATA_A57_828024, cortex_a57, 828024 |
| 483 | report_errata ERRATA_A57_829520, cortex_a57, 829520 |
| 484 | report_errata ERRATA_A57_833471, cortex_a57, 833471 |
| 485 | |
| 486 | ldp x8, x30, [sp], #16 |
| 487 | ret |
| 488 | endfunc cortex_a57_errata_report |
| 489 | #endif |
| 490 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 491 | /* --------------------------------------------- |
| 492 | * This function provides cortex_a57 specific |
| 493 | * register information for crash reporting. |
| 494 | * It needs to return with x6 pointing to |
| 495 | * a list of register names in ascii and |
| 496 | * x8 - x15 having values of registers to be |
| 497 | * reported. |
| 498 | * --------------------------------------------- |
| 499 | */ |
| 500 | .section .rodata.cortex_a57_regs, "aS" |
| 501 | cortex_a57_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 502 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 503 | |
| 504 | func cortex_a57_cpu_reg_dump |
| 505 | adr x6, cortex_a57_regs |
| 506 | mrs x8, CPUECTLR_EL1 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 507 | mrs x9, CPUMERRSR_EL1 |
| 508 | mrs x10, L2MERRSR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 509 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 510 | endfunc cortex_a57_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 511 | |
| 512 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 513 | declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ |
| 514 | cortex_a57_reset_func, \ |
| 515 | cortex_a57_core_pwr_dwn, \ |
| 516 | cortex_a57_cluster_pwr_dwn |