Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 30 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 31 | #include <asm_macros.S> |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 32 | #include <assert_macros.S> |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 33 | #include <bl_common.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 34 | #include <cortex_a57.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 35 | #include <cpu_macros.S> |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 36 | #include <debug.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 37 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 38 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 39 | /* --------------------------------------------- |
| 40 | * Disable L1 data cache and unified L2 cache |
| 41 | * --------------------------------------------- |
| 42 | */ |
| 43 | func cortex_a57_disable_dcache |
| 44 | mrs x1, sctlr_el3 |
| 45 | bic x1, x1, #SCTLR_C_BIT |
| 46 | msr sctlr_el3, x1 |
| 47 | isb |
| 48 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 49 | endfunc cortex_a57_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 50 | |
| 51 | /* --------------------------------------------- |
| 52 | * Disable all types of L2 prefetches. |
| 53 | * --------------------------------------------- |
| 54 | */ |
| 55 | func cortex_a57_disable_l2_prefetch |
| 56 | mrs x0, CPUECTLR_EL1 |
| 57 | orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 58 | mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK |
| 59 | orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK |
| 60 | bic x0, x0, x1 |
| 61 | msr CPUECTLR_EL1, x0 |
| 62 | isb |
Soby Mathew | 1604fa0 | 2014-09-22 12:15:26 +0100 | [diff] [blame] | 63 | dsb ish |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 64 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 65 | endfunc cortex_a57_disable_l2_prefetch |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 66 | |
| 67 | /* --------------------------------------------- |
| 68 | * Disable intra-cluster coherency |
| 69 | * --------------------------------------------- |
| 70 | */ |
| 71 | func cortex_a57_disable_smp |
| 72 | mrs x0, CPUECTLR_EL1 |
| 73 | bic x0, x0, #CPUECTLR_SMP_BIT |
| 74 | msr CPUECTLR_EL1, x0 |
| 75 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 76 | endfunc cortex_a57_disable_smp |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 77 | |
| 78 | /* --------------------------------------------- |
| 79 | * Disable debug interfaces |
| 80 | * --------------------------------------------- |
| 81 | */ |
| 82 | func cortex_a57_disable_ext_debug |
| 83 | mov x0, #1 |
| 84 | msr osdlr_el1, x0 |
| 85 | isb |
| 86 | dsb sy |
| 87 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 88 | endfunc cortex_a57_disable_ext_debug |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 89 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 90 | /* -------------------------------------------------- |
| 91 | * Errata Workaround for Cortex A57 Errata #806969. |
| 92 | * This applies only to revision r0p0 of Cortex A57. |
| 93 | * Inputs: |
| 94 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Soby Mathew | b5a6304 | 2015-01-29 12:00:58 +0000 | [diff] [blame] | 95 | * Clobbers : x0 - x5 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 96 | * -------------------------------------------------- |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 97 | */ |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 98 | func errata_a57_806969_wa |
| 99 | /* |
| 100 | * Compare x0 against revision r0p0 |
| 101 | */ |
| 102 | cbz x0, apply_806969 |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 103 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 104 | b print_revision_warning |
| 105 | #else |
| 106 | ret |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 107 | #endif |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 108 | apply_806969: |
| 109 | mrs x1, CPUACTLR_EL1 |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 110 | orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 111 | msr CPUACTLR_EL1, x1 |
| 112 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 113 | endfunc errata_a57_806969_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 114 | |
| 115 | |
| 116 | /* --------------------------------------------------- |
| 117 | * Errata Workaround for Cortex A57 Errata #813420. |
| 118 | * This applies only to revision r0p0 of Cortex A57. |
| 119 | * Inputs: |
| 120 | * x0: variant[4:7] and revision[0:3] of current cpu. |
Soby Mathew | b5a6304 | 2015-01-29 12:00:58 +0000 | [diff] [blame] | 121 | * Clobbers : x0 - x5 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 122 | * --------------------------------------------------- |
| 123 | */ |
| 124 | func errata_a57_813420_wa |
| 125 | /* |
| 126 | * Compare x0 against revision r0p0 |
| 127 | */ |
| 128 | cbz x0, apply_813420 |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 129 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 130 | b print_revision_warning |
| 131 | #else |
| 132 | ret |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 133 | #endif |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 134 | apply_813420: |
| 135 | mrs x1, CPUACTLR_EL1 |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 136 | orr x1, x1, #CPUACTLR_DCC_AS_DCCI |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 137 | msr CPUACTLR_EL1, x1 |
| 138 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 139 | endfunc errata_a57_813420_wa |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 140 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 141 | /* -------------------------------------------------------------------- |
| 142 | * Disable the over-read from the LDNP instruction. |
| 143 | * |
| 144 | * This applies to all revisions <= r1p2. The performance degradation |
| 145 | * observed with LDNP/STNP has been fixed on r1p3 and onwards. |
| 146 | * |
| 147 | * Inputs: |
| 148 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 149 | * Clobbers : x0 - x5, x30 |
| 150 | * --------------------------------------------------------------------- |
| 151 | */ |
| 152 | func a57_disable_ldnp_overread |
| 153 | /* |
| 154 | * Compare x0 against revision r1p2 |
| 155 | */ |
| 156 | cmp x0, #0x12 |
| 157 | b.ls disable_hint |
Soby Mathew | 6b28c57 | 2016-03-21 10:36:47 +0000 | [diff] [blame] | 158 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 159 | b print_revision_warning |
| 160 | #else |
| 161 | ret |
| 162 | #endif |
| 163 | disable_hint: |
| 164 | mrs x1, CPUACTLR_EL1 |
| 165 | orr x1, x1, #CPUACTLR_DIS_OVERREAD |
| 166 | msr CPUACTLR_EL1, x1 |
| 167 | ret |
| 168 | endfunc a57_disable_ldnp_overread |
| 169 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 170 | /* --------------------------------------------------- |
| 171 | * Errata Workaround for Cortex A57 Errata #826974. |
| 172 | * This applies only to revision <= r1p1 of Cortex A57. |
| 173 | * Inputs: |
| 174 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 175 | * Clobbers : x0 - x5 |
| 176 | * --------------------------------------------------- |
| 177 | */ |
| 178 | func errata_a57_826974_wa |
| 179 | /* |
| 180 | * Compare x0 against revision r1p1 |
| 181 | */ |
| 182 | cmp x0, #0x11 |
| 183 | b.ls apply_826974 |
| 184 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
| 185 | b print_revision_warning |
| 186 | #else |
| 187 | ret |
| 188 | #endif |
| 189 | apply_826974: |
| 190 | mrs x1, CPUACTLR_EL1 |
| 191 | orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB |
| 192 | msr CPUACTLR_EL1, x1 |
| 193 | ret |
| 194 | endfunc errata_a57_826974_wa |
| 195 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 196 | /* --------------------------------------------------- |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 197 | * Errata Workaround for Cortex A57 Errata #826977. |
| 198 | * This applies only to revision <= r1p1 of Cortex A57. |
| 199 | * Inputs: |
| 200 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 201 | * Clobbers : x0 - x5 |
| 202 | * --------------------------------------------------- |
| 203 | */ |
| 204 | func errata_a57_826977_wa |
| 205 | /* |
| 206 | * Compare x0 against revision r1p1 |
| 207 | */ |
| 208 | cmp x0, #0x11 |
| 209 | b.ls apply_826977 |
| 210 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
| 211 | b print_revision_warning |
| 212 | #else |
| 213 | ret |
| 214 | #endif |
| 215 | apply_826977: |
| 216 | mrs x1, CPUACTLR_EL1 |
| 217 | orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE |
| 218 | msr CPUACTLR_EL1, x1 |
| 219 | ret |
| 220 | endfunc errata_a57_826977_wa |
| 221 | |
| 222 | /* --------------------------------------------------- |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 223 | * Errata Workaround for Cortex A57 Errata #828024. |
| 224 | * This applies only to revision <= r1p1 of Cortex A57. |
| 225 | * Inputs: |
| 226 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 227 | * Clobbers : x0 - x5 |
| 228 | * --------------------------------------------------- |
| 229 | */ |
| 230 | func errata_a57_828024_wa |
| 231 | /* |
| 232 | * Compare x0 against revision r1p1 |
| 233 | */ |
| 234 | cmp x0, #0x11 |
| 235 | b.ls apply_828024 |
| 236 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
| 237 | b print_revision_warning |
| 238 | #else |
| 239 | ret |
| 240 | #endif |
| 241 | apply_828024: |
| 242 | mrs x1, CPUACTLR_EL1 |
| 243 | /* |
| 244 | * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 |
| 245 | * instructions here because the resulting bitmask doesn't fit in a |
| 246 | * 16-bit value so it cannot be encoded in a single instruction. |
| 247 | */ |
| 248 | orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA |
| 249 | orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) |
| 250 | msr CPUACTLR_EL1, x1 |
| 251 | ret |
| 252 | endfunc errata_a57_828024_wa |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 253 | |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 254 | /* --------------------------------------------------- |
| 255 | * Errata Workaround for Cortex A57 Errata #829520. |
| 256 | * This applies only to revision <= r1p2 of Cortex A57. |
| 257 | * Inputs: |
| 258 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 259 | * Clobbers : x0 - x5 |
| 260 | * --------------------------------------------------- |
| 261 | */ |
| 262 | func errata_a57_829520_wa |
| 263 | /* |
| 264 | * Compare x0 against revision r1p2 |
| 265 | */ |
| 266 | cmp x0, #0x12 |
| 267 | b.ls apply_829520 |
| 268 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
| 269 | b print_revision_warning |
| 270 | #else |
| 271 | ret |
| 272 | #endif |
| 273 | apply_829520: |
| 274 | mrs x1, CPUACTLR_EL1 |
| 275 | orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR |
| 276 | msr CPUACTLR_EL1, x1 |
| 277 | ret |
| 278 | endfunc errata_a57_829520_wa |
| 279 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 280 | /* --------------------------------------------------- |
| 281 | * Errata Workaround for Cortex A57 Errata #833471. |
| 282 | * This applies only to revision <= r1p2 of Cortex A57. |
| 283 | * Inputs: |
| 284 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 285 | * Clobbers : x0 - x5 |
| 286 | * --------------------------------------------------- |
| 287 | */ |
| 288 | func errata_a57_833471_wa |
| 289 | /* |
| 290 | * Compare x0 against revision r1p2 |
| 291 | */ |
| 292 | cmp x0, #0x12 |
| 293 | b.ls apply_833471 |
| 294 | #if LOG_LEVEL >= LOG_LEVEL_VERBOSE |
| 295 | b print_revision_warning |
| 296 | #else |
| 297 | ret |
| 298 | #endif |
| 299 | apply_833471: |
| 300 | mrs x1, CPUACTLR_EL1 |
| 301 | orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH |
| 302 | msr CPUACTLR_EL1, x1 |
| 303 | ret |
| 304 | endfunc errata_a57_833471_wa |
| 305 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 306 | /* ------------------------------------------------- |
| 307 | * The CPU Ops reset function for Cortex-A57. |
Soby Mathew | b5a6304 | 2015-01-29 12:00:58 +0000 | [diff] [blame] | 308 | * Clobbers: x0-x5, x15, x19, x30 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 309 | * ------------------------------------------------- |
| 310 | */ |
| 311 | func cortex_a57_reset_func |
| 312 | mov x19, x30 |
| 313 | mrs x0, midr_el1 |
| 314 | |
| 315 | /* |
| 316 | * Extract the variant[20:23] and revision[0:3] from x0 |
Soby Mathew | b5a6304 | 2015-01-29 12:00:58 +0000 | [diff] [blame] | 317 | * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. |
| 318 | * First extract x0[16:23] to x15[0:7] and zero fill the rest. |
| 319 | * Then extract x0[0:3] into x15[0:3] retaining other bits. |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 320 | */ |
Soby Mathew | b5a6304 | 2015-01-29 12:00:58 +0000 | [diff] [blame] | 321 | ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS) |
| 322 | bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 323 | |
| 324 | #if ERRATA_A57_806969 |
Soby Mathew | b5a6304 | 2015-01-29 12:00:58 +0000 | [diff] [blame] | 325 | mov x0, x15 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 326 | bl errata_a57_806969_wa |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 327 | #endif |
| 328 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 329 | #if ERRATA_A57_813420 |
Soby Mathew | b5a6304 | 2015-01-29 12:00:58 +0000 | [diff] [blame] | 330 | mov x0, x15 |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 331 | bl errata_a57_813420_wa |
| 332 | #endif |
Yatharth Kochar | 36433d1 | 2014-11-20 18:09:41 +0000 | [diff] [blame] | 333 | |
Sandrine Bailleux | d481759 | 2016-01-13 14:57:38 +0000 | [diff] [blame] | 334 | #if A57_DISABLE_NON_TEMPORAL_HINT |
| 335 | mov x0, x15 |
| 336 | bl a57_disable_ldnp_overread |
| 337 | #endif |
| 338 | |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 339 | #if ERRATA_A57_826974 |
| 340 | mov x0, x15 |
| 341 | bl errata_a57_826974_wa |
| 342 | #endif |
| 343 | |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 344 | #if ERRATA_A57_826977 |
| 345 | mov x0, x15 |
| 346 | bl errata_a57_826977_wa |
| 347 | #endif |
| 348 | |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 349 | #if ERRATA_A57_828024 |
| 350 | mov x0, x15 |
| 351 | bl errata_a57_828024_wa |
| 352 | #endif |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 353 | |
| 354 | #if ERRATA_A57_829520 |
| 355 | mov x0, x15 |
| 356 | bl errata_a57_829520_wa |
| 357 | #endif |
| 358 | |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 359 | #if ERRATA_A57_833471 |
| 360 | mov x0, x15 |
| 361 | bl errata_a57_833471_wa |
| 362 | #endif |
| 363 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 364 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 365 | * Enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 366 | * --------------------------------------------- |
| 367 | */ |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 368 | mrs x0, CPUECTLR_EL1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 369 | orr x0, x0, #CPUECTLR_SMP_BIT |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 370 | msr CPUECTLR_EL1, x0 |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 371 | isb |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 372 | ret x19 |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 373 | endfunc cortex_a57_reset_func |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 374 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 375 | /* ---------------------------------------------------- |
| 376 | * The CPU Ops core power down function for Cortex-A57. |
| 377 | * ---------------------------------------------------- |
| 378 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 379 | func cortex_a57_core_pwr_dwn |
| 380 | mov x18, x30 |
| 381 | |
| 382 | /* --------------------------------------------- |
| 383 | * Turn off caches. |
| 384 | * --------------------------------------------- |
| 385 | */ |
| 386 | bl cortex_a57_disable_dcache |
| 387 | |
| 388 | /* --------------------------------------------- |
| 389 | * Disable the L2 prefetches. |
| 390 | * --------------------------------------------- |
| 391 | */ |
| 392 | bl cortex_a57_disable_l2_prefetch |
| 393 | |
| 394 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 395 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 396 | * --------------------------------------------- |
| 397 | */ |
| 398 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 399 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 400 | |
| 401 | /* --------------------------------------------- |
| 402 | * Come out of intra cluster coherency |
| 403 | * --------------------------------------------- |
| 404 | */ |
| 405 | bl cortex_a57_disable_smp |
| 406 | |
| 407 | /* --------------------------------------------- |
| 408 | * Force the debug interfaces to be quiescent |
| 409 | * --------------------------------------------- |
| 410 | */ |
| 411 | mov x30, x18 |
| 412 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 413 | endfunc cortex_a57_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 414 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 415 | /* ------------------------------------------------------- |
| 416 | * The CPU Ops cluster power down function for Cortex-A57. |
| 417 | * ------------------------------------------------------- |
| 418 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 419 | func cortex_a57_cluster_pwr_dwn |
| 420 | mov x18, x30 |
| 421 | |
| 422 | /* --------------------------------------------- |
| 423 | * Turn off caches. |
| 424 | * --------------------------------------------- |
| 425 | */ |
| 426 | bl cortex_a57_disable_dcache |
| 427 | |
| 428 | /* --------------------------------------------- |
| 429 | * Disable the L2 prefetches. |
| 430 | * --------------------------------------------- |
| 431 | */ |
| 432 | bl cortex_a57_disable_l2_prefetch |
| 433 | |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 434 | #if !SKIP_A57_L1_FLUSH_PWR_DWN |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 435 | /* ------------------------------------------------- |
| 436 | * Flush the L1 caches. |
| 437 | * ------------------------------------------------- |
| 438 | */ |
| 439 | mov x0, #DCCISW |
| 440 | bl dcsw_op_level1 |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 441 | #endif |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 442 | /* --------------------------------------------- |
| 443 | * Disable the optional ACP. |
| 444 | * --------------------------------------------- |
| 445 | */ |
| 446 | bl plat_disable_acp |
| 447 | |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 448 | /* ------------------------------------------------- |
| 449 | * Flush the L2 caches. |
| 450 | * ------------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 451 | */ |
| 452 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 453 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 454 | |
| 455 | /* --------------------------------------------- |
| 456 | * Come out of intra cluster coherency |
| 457 | * --------------------------------------------- |
| 458 | */ |
| 459 | bl cortex_a57_disable_smp |
| 460 | |
| 461 | /* --------------------------------------------- |
| 462 | * Force the debug interfaces to be quiescent |
| 463 | * --------------------------------------------- |
| 464 | */ |
| 465 | mov x30, x18 |
| 466 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 467 | endfunc cortex_a57_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 468 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 469 | /* --------------------------------------------- |
| 470 | * This function provides cortex_a57 specific |
| 471 | * register information for crash reporting. |
| 472 | * It needs to return with x6 pointing to |
| 473 | * a list of register names in ascii and |
| 474 | * x8 - x15 having values of registers to be |
| 475 | * reported. |
| 476 | * --------------------------------------------- |
| 477 | */ |
| 478 | .section .rodata.cortex_a57_regs, "aS" |
| 479 | cortex_a57_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 480 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 481 | |
| 482 | func cortex_a57_cpu_reg_dump |
| 483 | adr x6, cortex_a57_regs |
| 484 | mrs x8, CPUECTLR_EL1 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 485 | mrs x9, CPUMERRSR_EL1 |
| 486 | mrs x10, L2MERRSR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 487 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 488 | endfunc cortex_a57_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 489 | |
| 490 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 491 | declare_cpu_ops cortex_a57, CORTEX_A57_MIDR |