Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Manish V Badarkhe | 01e9dd2 | 2020-08-04 17:13:14 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
Antonio Nino Diaz | a320ecd | 2019-01-15 14:19:50 +0000 | [diff] [blame] | 6 | |
Manish V Badarkhe | 01e9dd2 | 2020-08-04 17:13:14 +0100 | [diff] [blame] | 7 | #include <lib/smccc.h> |
Antonio Nino Diaz | a320ecd | 2019-01-15 14:19:50 +0000 | [diff] [blame] | 8 | #include <platform_def.h> |
Manish V Badarkhe | 01e9dd2 | 2020-08-04 17:13:14 +0100 | [diff] [blame] | 9 | #include <services/arm_arch_svc.h> |
| 10 | |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 11 | #include <plat/arm/common/plat_arm.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 12 | |
| 13 | /* |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 14 | * Table of memory regions for different BL stages to map using the MMU. |
Roberto Vargas | 344ff02 | 2018-10-19 16:44:18 +0100 | [diff] [blame] | 15 | * This doesn't include Trusted SRAM as setup_page_tables() already takes care |
| 16 | * of mapping it. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 17 | */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 18 | #ifdef IMAGE_BL1 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 19 | const mmap_region_t plat_arm_mmap[] = { |
| 20 | ARM_MAP_SHARED_RAM, |
Soby Mathew | 9427357 | 2018-03-07 11:32:04 +0000 | [diff] [blame] | 21 | V2M_MAP_FLASH0_RW, |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 22 | V2M_MAP_IOFPGA, |
| 23 | CSS_MAP_DEVICE, |
| 24 | SOC_CSS_MAP_DEVICE, |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 25 | #if TRUSTED_BOARD_BOOT |
Sandrine Bailleux | d9160a5 | 2017-05-26 15:48:10 +0100 | [diff] [blame] | 26 | /* Map DRAM to authenticate NS_BL2U image. */ |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 27 | ARM_MAP_NS_DRAM1, |
| 28 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 29 | {0} |
| 30 | }; |
| 31 | #endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 32 | #ifdef IMAGE_BL2 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 33 | const mmap_region_t plat_arm_mmap[] = { |
| 34 | ARM_MAP_SHARED_RAM, |
Soby Mathew | 9427357 | 2018-03-07 11:32:04 +0000 | [diff] [blame] | 35 | V2M_MAP_FLASH0_RW, |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 36 | #ifdef PLAT_ARM_MEM_PROT_ADDR |
| 37 | ARM_V2M_MAP_MEM_PROTECT, |
| 38 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 39 | V2M_MAP_IOFPGA, |
| 40 | CSS_MAP_DEVICE, |
| 41 | SOC_CSS_MAP_DEVICE, |
| 42 | ARM_MAP_NS_DRAM1, |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 43 | #ifdef __aarch64__ |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 44 | ARM_MAP_DRAM2, |
| 45 | #endif |
Sandrine Bailleux | b260c3a | 2017-08-30 10:59:22 +0100 | [diff] [blame] | 46 | #ifdef SPD_tspd |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 47 | ARM_MAP_TSP_SEC_MEM, |
Sandrine Bailleux | b260c3a | 2017-08-30 10:59:22 +0100 | [diff] [blame] | 48 | #endif |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 49 | #ifdef SPD_opteed |
Soby Mathew | 874fc9e | 2017-09-01 13:43:50 +0100 | [diff] [blame] | 50 | ARM_MAP_OPTEE_CORE_MEM, |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 51 | ARM_OPTEE_PAGEABLE_LOAD_MEM, |
| 52 | #endif |
Louis Mayencourt | 3e7c38a | 2019-07-31 15:03:44 +0100 | [diff] [blame] | 53 | #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3 |
| 54 | ARM_MAP_BL1_RW, |
| 55 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 56 | {0} |
| 57 | }; |
| 58 | #endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 59 | #ifdef IMAGE_BL2U |
Yatharth Kochar | 3a11eda | 2015-10-14 15:28:11 +0100 | [diff] [blame] | 60 | const mmap_region_t plat_arm_mmap[] = { |
| 61 | ARM_MAP_SHARED_RAM, |
| 62 | CSS_MAP_DEVICE, |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 63 | CSS_MAP_SCP_BL2U, |
| 64 | V2M_MAP_IOFPGA, |
Yatharth Kochar | 3a11eda | 2015-10-14 15:28:11 +0100 | [diff] [blame] | 65 | SOC_CSS_MAP_DEVICE, |
| 66 | {0} |
| 67 | }; |
| 68 | #endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 69 | #ifdef IMAGE_BL31 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 70 | const mmap_region_t plat_arm_mmap[] = { |
| 71 | ARM_MAP_SHARED_RAM, |
| 72 | V2M_MAP_IOFPGA, |
| 73 | CSS_MAP_DEVICE, |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 74 | #ifdef PLAT_ARM_MEM_PROT_ADDR |
| 75 | ARM_V2M_MAP_MEM_PROTECT, |
| 76 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 77 | SOC_CSS_MAP_DEVICE, |
| 78 | {0} |
| 79 | }; |
| 80 | #endif |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 81 | #ifdef IMAGE_BL32 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 82 | const mmap_region_t plat_arm_mmap[] = { |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 83 | #ifndef __aarch64__ |
Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 84 | ARM_MAP_SHARED_RAM, |
Roberto Vargas | 550eb08 | 2018-01-05 16:00:05 +0000 | [diff] [blame] | 85 | #ifdef PLAT_ARM_MEM_PROT_ADDR |
| 86 | ARM_V2M_MAP_MEM_PROTECT, |
| 87 | #endif |
Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 88 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 89 | V2M_MAP_IOFPGA, |
| 90 | CSS_MAP_DEVICE, |
| 91 | SOC_CSS_MAP_DEVICE, |
| 92 | {0} |
| 93 | }; |
| 94 | #endif |
| 95 | |
| 96 | ARM_CASSERT_MMAP |
Manish V Badarkhe | 01e9dd2 | 2020-08-04 17:13:14 +0100 | [diff] [blame] | 97 | |
| 98 | /***************************************************************************** |
| 99 | * plat_is_smccc_feature_available() - This function checks whether SMCCC |
| 100 | * feature is availabile for platform. |
| 101 | * @fid: SMCCC function id |
| 102 | * |
| 103 | * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and |
| 104 | * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. |
| 105 | *****************************************************************************/ |
| 106 | int32_t plat_is_smccc_feature_available(u_register_t fid) |
| 107 | { |
| 108 | switch (fid) { |
| 109 | case SMCCC_ARCH_SOC_ID: |
| 110 | return SMC_ARCH_CALL_SUCCESS; |
| 111 | default: |
| 112 | return SMC_ARCH_CALL_NOT_SUPPORTED; |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | /* Get SOC version */ |
| 117 | int32_t plat_get_soc_version(void) |
| 118 | { |
| 119 | return (int32_t) |
| 120 | ((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT) |
| 121 | | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT) |
| 122 | | JUNO_SOC_ID); |
| 123 | } |
| 124 | |
| 125 | /* Get SOC revision */ |
| 126 | int32_t plat_get_soc_revision(void) |
| 127 | { |
| 128 | unsigned int sys_id; |
| 129 | |
| 130 | sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); |
| 131 | return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) & |
| 132 | V2M_SYS_ID_REV_MASK); |
| 133 | } |